Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date         : Thu Apr 11 18:42:32 2019
| Host         : DESKTOP-8QFGS52 running 64-bit major release  (build 9200)
| Command      : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
| Design       : CPU9bits
| Device       : xc7k160ti
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets                            |     9 |
| Unused register locations in slices containing registers |    61 |
+----------------------------------------------------------+-------+


2. Histogram
------------

+--------+--------------+
| Fanout | Control Sets |
+--------+--------------+
|      9 |            8 |
|    16+ |            1 |
+--------+--------------+


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |               0 |            0 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |              91 |           35 |
| Yes          | No                    | No                     |               0 |            0 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |              72 |           23 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+----------------+-------------------------+------------------+------------------+----------------+
|  Clock Signal  |      Enable Signal      | Set/Reset Signal | Slice Load Count | Bel Load Count |
+----------------+-------------------------+------------------+------------------+----------------+
|  clk_IBUF_BUFG | pipe2/Dout_reg[6]_2[0]  | reset_IBUF       |                5 |              9 |
|  clk_IBUF_BUFG | pipe2/Dout_reg[6]_1[0]  | reset_IBUF       |                2 |              9 |
|  clk_IBUF_BUFG | pipe2/E[0]              | reset_IBUF       |                2 |              9 |
|  clk_IBUF_BUFG | pipe2/Dout_reg[6]_3[0]  | reset_IBUF       |                4 |              9 |
|  clk_IBUF_BUFG | pipe1/Dout_reg[43]_0[0] | reset_IBUF       |                2 |              9 |
|  clk_IBUF_BUFG | pipe1/Dout_reg[1]_0[0]  | reset_IBUF       |                2 |              9 |
|  clk_IBUF_BUFG | pipe1/Dout_reg[1]_1[0]  | reset_IBUF       |                2 |              9 |
|  clk_IBUF_BUFG | pipe1/E[0]              | reset_IBUF       |                4 |              9 |
|  clk_IBUF_BUFG |                         | reset_IBUF       |               35 |             91 |
+----------------+-------------------------+------------------+------------------+----------------+