`timescale 1ns / 1ps

module dataMemory(
    input wire clk, writeEnable,
    input wire [8:0] address, writeData,
    output reg [8:0] readData
    );
    
    reg [8:0] memory [1:0];   // Maximum of 512 memory locations
                                // Vivado will give warnings of unconnected ports on the "address" bus if they are unused
    
    initial begin



        //Equation Solver Memory

        memory[0] <= 9'b000000001;
        memory[1] <= 9'b000000010;



        // String Compare Memory

//         memory[0] <= 9'b000000100;
//         memory[1] <= 9'b000001000;
//         memory[2] <= 9'b000001100;
//         memory[3] <= 9'b010101010;
//         memory[4] <= 9'b000001111;
//         memory[5] <= 9'b000000100;
//         memory[6] <= 9'b000000000;
//         memory[7] <= 9'b000000111;
//         memory[8] <= 9'b000001111;
//         memory[9] <= 9'b000000110;
//        memory[10] <= 9'b000000010;
//        memory[11] <= 9'b000000000;
//        memory[12] <= 9'b000000000;
//        memory[13] <= 9'b000000000;
//        memory[14] <= 9'b000000000;
//        memory[15] <= 9'b000000000;



        // Bubble Sort Initial Memory
        
//         memory[0] <= 9'b000010110;
//         memory[1] <= 9'b000100010;
//         memory[2] <= 9'b000100000;
//         memory[3] <= 9'b010001000;
//         memory[4] <= 9'b010010000;
//         memory[5] <= 9'b010011000;
//         memory[6] <= 9'b101001000;
//         memory[7] <= 9'b101001010;
//         memory[8] <= 9'b000100011;
//         memory[9] <= 9'b101001001;
//        memory[10] <= 9'b011001001;
//        memory[11] <= 9'b001001000;
//        memory[12] <= 9'b101001001;
//        memory[13] <= 9'b011101000;
//        memory[14] <= 9'b110001010;
//        memory[15] <= 9'b000100001;
//        memory[16] <= 9'b100110100;
//        memory[17] <= 9'b000001001;
//        memory[18] <= 9'b011001001;
//        memory[19] <= 9'b000110010;
//        memory[20] <= 9'b000000001;
//        memory[21] <= 9'b000111010;
//        memory[22] <= 9'b101011110;
//        memory[23] <= 9'b011111100;



        // Binary Search Memory

//         memory[0] <= 9'b000000000;
//         memory[1] <= 9'b000000111;
//         memory[2] <= 9'b000000001;
//         memory[3] <= 9'b000000010;
//         memory[4] <= 9'b000000011;
//         memory[5] <= 9'b000000100;
//         memory[6] <= 9'b000000101;
//         memory[7] <= 9'b000000110;
//         memory[8] <= 9'b000000111;
//         memory[9] <= 9'b000001000;
//        memory[10] <= 9'b000001001;
//        memory[11] <= 9'b000001010;
//        memory[12] <= 9'b000001011;
//        memory[13] <= 9'b000001100;
//        memory[14] <= 9'b000001101;
//        memory[15] <= 9'b000001110;
//        memory[16] <= 9'b000001111;
//        memory[17] <= 9'b000010000;
//        memory[18] <= 9'b000010001;
//        memory[19] <= 9'b000010010;



        // Program 1 Test Data

         memory[0] <= 9'd100;
         memory[1] <= 9'd58;
         memory[2] <= 9'd6;
         memory[3] <= 9'd12;
         memory[4] <= 9'b110110000; // -80
         memory[5] <= 9'd17;
         memory[6] <= 9'b111011011; // -37
         memory[7] <= 9'd25;
         memory[8] <= -9'd83; // -83
         memory[9] <= -9'd98; // -98
        memory[10] <= -9'd98; // -98
        memory[11] <= -9'd74; // -74
        memory[12] <= 9'd70;
        memory[13] <= -9'd38; // -38
        memory[14] <= 9'd52;
        memory[15] <= -9'd96; // -96
        memory[16] <= -9'd32; // -32
        memory[17] <= -9'd93; // -93
        memory[18] <= -9'd40; // -40
        memory[19] <= 9'd59;
        memory[20] <= 9'd10;
        memory[21] <= 9'd81;
        memory[22] <= -9'd23; // -28
        memory[23] <=- 9'd99; // -99
        memory[24] <= -9'd41; // -41
        memory[25] <= 9'd33;
        memory[26] <= 9'd98;
        memory[27] <= 9'd73;
        memory[28] <= -9'd1; // -1
        memory[29] <= 9'd28;
        memory[30] <= 9'd5;
        memory[31] <= -9'd74; // -74
        memory[32] <= -9'd41; // -41
        memory[33] <= 9'd41;
        memory[34] <= 9'd39;
        memory[35] <= 9'd62;
        memory[36] <= 9'd19;
        memory[37] <= -9'd40; // -40
        memory[38] <= -9'd8; // -8
        memory[39] <= 9'd92;
        memory[40] <= 9'd37;
        memory[41] <= 9'd50;
        memory[42] <= -9'd72; // -72
        memory[43] <= -9'd5; // -5
        memory[44] <= 9'd19;
        memory[45] <= 9'd58;
        memory[46] <= -9'd13; // -13
        memory[47] <= 9'd0;
        memory[48] <= -9'd97; // -97
        memory[49] <= 9'd54;
        memory[50] <= -9'd17; // -17
        memory[51] <= -9'd83; // -83
        memory[52] <= 9'd53;
        memory[53] <= 9'd82;
        memory[54] <= -9'd94; // -94
        memory[55] <= -9'd77; // -77
        memory[56] <= -9'd74; // -74
        memory[57] <= -9'd52; // -52
        memory[58] <= 9'd85;
        memory[59] <= -9'd65; // -65
        memory[60] <= -9'd10; // -10
        memory[61] <= -9'd45; // -45
        memory[62] <= -9'd92; // -92
        memory[63] <= -9'd30; // -30
        memory[64] <= 9'd18;
        memory[65] <= -9'd95; // -95
        memory[66] <= -9'd27; // -27
        memory[67] <= -9'd74; // -74
        memory[68] <= 9'd62;
        memory[69] <= 9'd64;
        memory[70] <= -9'd9; // -9
        memory[71] <= 9'd66;
        memory[72] <= -9'd71; // -71
        memory[73] <= -9'd31; // -31
        memory[74] <= 9'd34;
        memory[75] <= 9'd12;
        memory[76] <= 9'd3;
        memory[77] <= 9'd82;
        memory[78] <= 9'd13;
        memory[79] <= -9'd78; // -78
        memory[80] <= -9'd8; // -8
        memory[81] <= 9'd88;
        memory[82] <= 9'd42;
        memory[83] <= 9'd42;
        memory[84] <= 9'd21;
        memory[85] <= -9'd44; // -44
        memory[86] <= 9'd30;
        memory[87] <= -9'd93; // -93
        memory[88] <= 9'd2;
        memory[89] <= -9'd34; // -34
        memory[90] <= 9'd92;
        memory[91] <= -9'd45; // -45
        memory[92] <= 9'd26;
        memory[93] <= -9'd79; // -79
        memory[94] <= 9'd43;
        memory[95] <= -9'd25; // -25
        memory[96] <= -9'd24; // -24
        memory[97] <= -9'd25; // -25
        memory[98] <= -9'd19; // -19
        memory[99] <= -9'd49; // -49
       memory[100] <= -9'd8; // -8



        // Program 2 Test Data

//         memory[0] <= 9'd4;
//         memory[1] <= 9'd15;
//         memory[2] <= 9'b000001100;
//         memory[3] <= 9'b010101010;
//         memory[4] <= 9'h68; // h
//         memory[5] <= 9'h65; // e
//         memory[6] <= 9'h6C; // l
//         memory[7] <= 9'h6C; // l
//         memory[8] <= 9'h6F; // o
//         memory[9] <= 9'h20; // <space>
//        memory[10] <= 9'h77; // w
//        memory[11] <= 9'h6F; // o
//        memory[12] <= 9'h72; // r
//        memory[13] <= 9'h6C; // l
//        memory[14] <= 9'h64; // d
//        memory[15] <= 9'h68; // h
//        memory[16] <= 9'h65; // e
//        memory[17] <= 9'h6C; // l
//        memory[18] <= 9'h6C; // l
//        memory[19] <= 9'h6F; // o
//        memory[20] <= 9'h20; // <space>
//        memory[21] <= 9'h77; // w
//        memory[22] <= 9'h6F; // o
//        memory[23] <= 9'h72; // r
//        memory[24] <= 9'h6C; // l
//        memory[25] <= 9'h64; // d



        // Program 3 Test Data

//         memory[0] <= 9'd25; // 25
//         memory[1] <= -9'd3; // -3


    end

    always @ (posedge clk)
    begin
        if(writeEnable == 1'b1)
            memory[address] <= writeData;
        else
            readData <= memory[address];
    end      
endmodule

module dataMemory_tb();
    reg clk, writeEnable;
    reg [8:0] address, writeData;
    wire [8:0] readData;
    
    always
        #5 clk = ~clk; // Period to be determined
    
    dataMemory dM0(
        .clk(clk),
        .writeEnable(writeEnable),
        .writeData(writeData),
        .address(address),
        .readData(readData)
    );
    
    initial
    begin
        clk = 1'b0;
        writeEnable = 1'b0;
        address = 9'b000000000;
        writeData = 9'b010101010;
        #5
        address = 9'b000000100;
        writeData = 9'b010101010;
        #10
        writeEnable = 1'b1;
        address = 9'b000000000;
        writeData = 9'b010101010;
        #10
        address = 9'b000000001;
        writeData = 9'b000001111;
        #10
        address = 9'b000000010;
        writeData = 9'b000000101;
        #10
        writeEnable = 1'b0;
        address = 9'b001000000;
        writeData = 9'b010101010;
        #10
        address = 9'b001000001;
        writeData = 9'b000001111;
        #10
        address = 9'b000011010;
        writeData = 9'b000000101;
        #10
        writeEnable = 1'b1;
        address = 9'b100111000;
        writeData = 9'b010101010;
        #10
        address = 9'b100100001;
        writeData = 9'b000001111;
        #10
        address = 9'b110000010;
        writeData = 9'b000000101;
        #10
        address = 9'b111110011;
        writeData = 9'b000000011;
        #10
        address = 9'b00000010;
        writeData = 9'b000001101;
        #5
        $finish;
    end
endmodule