write_d[8:0] write_d[8:0] w_idx[1:0] w_idx[1:0] op0_idx[1:0] op0_idx[1:0] op1_idx[1:0] op1_idx[1:0] reset reset clk clk enable enable op0[8:0] op0[8:0] op1[8:0] op1[8:0] decOut[3:0] decOut[3:0] r0_out[8:0] r0_out[8:0] r1_out[8:0] r1_out[8:0] r2_out[8:0] r2_out[8:0] r3_out[8:0] r3_out[8:0]