`timescale 1ns / 1ps

module instructionMemory(
    input wire clk,
    input wire [8:0] address,
    output reg [8:0] readData
    );
    
    reg [8:0] memory [512:0];
    
    initial begin
        //Equation Solver
        memory[0] <= 9'b000000000;
        memory[1] <= 9'b000100000; //load
        memory[2] <= 9'b000101000; //load
        memory[3] <= 9'b010100010; //add
        memory[4] <= 9'b111100000; //shift left
        memory[5] <= 9'b111100000; //shift left
        
        //Testing all instructions
        memory[6] <= 9'b010100011; //sub
        memory[7] <= 9'b011001011; //addi
        memory[8] <= 9'b011110000; //slt
        memory[9] <= 9'b110111000; //nor
        memory[10] <= 9'b111011000; //or
        memory[11] <= 9'b111011001; //and
        memory[12] <= 9'b111111000; //sll
        memory[13] <= 9'b111111001; //srl
  //      memory[14] <= 9'b100101100; //j
        memory[14] <= 9'b110001001; //beq
        memory[15] <= 9'b100001000; //jr
        
        
        
        
        memory[16] <= 9'b000000000;
        
        
    end
    
    
    always@(address)begin
        readData <= memory[address];
    end
endmodule


module instructionMemory_tb();
    reg clk;
    reg [8:0] address;
    wire [8:0] readData;
    
        initial begin
        clk = 1'b0;
    end
    always begin
        #5 clk = ~clk; // Period to be determined
    end
    
    instructionMemory iM0(
        .clk(clk),
        .address(address),
        .readData(readData)
    );
    
    initial begin
        #10
        address = 9'b000000000;
        #5
        address = 9'b000000001;
        #5
        address = 9'b000000010;
        #5
        address = 9'b000000011;
        #5
        address = 9'b000000100;
        #5
        address = 9'b000000101;
        #5
        address = 9'b000000111;
        #5
        $finish;
    end
endmodule