#----------------------------------------------------------- # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # Start of session at: Sat Apr 6 16:04:16 2019 # Process ID: 22928 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1 # Command line: vivado.exe -log CPU9bits_tb.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.vds # Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou #----------------------------------------------------------- source CPU9bits_tb.tcl -notrace Command: synth_design -top CPU9bits_tb -part xc7k160tifbg484-2L Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 23288 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 362.297 ; gain = 100.883 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'CPU9bits_tb' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:204] WARNING: [Synth 8-85] always block has no event control specified [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:209] INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:266] INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766] INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766] INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396] INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:401] INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396] INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325] INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:331] INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325] INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1334] INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1399] INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676] INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676] INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1399] INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1334] INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713] INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713] INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632] INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632] INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:876] INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:876] INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:950] INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:950] INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:913] INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:913] INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309] INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309] INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1448] INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1448] INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524] INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:530] INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524] INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:13] INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1019] INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1019] INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339] INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:345] INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339] INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] WARNING: [Synth 8-350] instance 'CPU9bits0' of module 'CPU9bits' requires 4 connections, but only 3 given [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:212] INFO: [Synth 8-6155] done synthesizing module 'CPU9bits_tb' (28#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:204] WARNING: [Synth 8-3331] design RegFile has unconnected port enable WARNING: [Synth 8-3331] design dataMemory has unconnected port address[8] WARNING: [Synth 8-3331] design dataMemory has unconnected port address[7] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.582 ; gain = 157.168 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.582 ; gain = 157.168 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k160tifbg484-2L --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.582 ; gain = 157.168 INFO: [Device 21-403] Loading part xc7k160tifbg484-2L --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 418.582 ; gain = 157.168 --------------------------------------------------------------------------------- INFO: [Synth 8-223] decloning instance 'CPU9bits0/SE1' (sign_extend_3bit) to 'CPU9bits0/SE3' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 162 +---Registers : 9 Bit Registers := 10 +---RAMs : 909 Bit RAMs := 1 +---Muxes : 4 Input 9 Bit Muxes := 5 2 Input 9 Bit Muxes := 8 4 Input 4 Bit Muxes := 2 16 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 16 Input 3 Bit Muxes := 1 16 Input 2 Bit Muxes := 1 8 Input 2 Bit Muxes := 1 16 Input 1 Bit Muxes := 7 2 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module dataMemory Detailed RTL Component Info : +---Registers : 9 Bit Registers := 1 +---RAMs : 909 Bit RAMs := 1 Module decoder Detailed RTL Component Info : +---Muxes : 4 Input 4 Bit Muxes := 1 Module register Detailed RTL Component Info : +---Registers : 9 Bit Registers := 1 Module mux_4_1 Detailed RTL Component Info : +---Muxes : 4 Input 9 Bit Muxes := 1 Module add_1bit Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 2 Module mux_2_1 Detailed RTL Component Info : +---Muxes : 2 Input 9 Bit Muxes := 1 Module ControlUnit Detailed RTL Component Info : +---Muxes : 16 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 16 Input 3 Bit Muxes := 1 16 Input 2 Bit Muxes := 1 16 Input 1 Bit Muxes := 7 Module bit1_mux_2_1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module CPU9bits Detailed RTL Component Info : +---Muxes : 4 Input 9 Bit Muxes := 1 8 Input 2 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 600 (col length:100) BRAMs: 650 (col length: RAMB18 100 RAMB36 50) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 586.449 ; gain = 325.035 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- ROM: +------------------+------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------------+------------+---------------+----------------+ |instructionMemory | p_0_out | 64x9 | LUT | |CPU9bits_tb | p_0_out | 64x9 | LUT | +------------------+------------+---------------+----------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 586.449 ; gain = 325.035 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 586.449 ; gain = 325.035 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +-+-----+------+ | |Cell |Count | +-+-----+------+ +-+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 0| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 5 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035 Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 674.711 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 70 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 674.711 ; gain = 426.559 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 674.711 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Sat Apr 6 16:04:50 2019...