`timescale 1ns / 1ps

module adder_1bit(
    input wire A,
    input wire B,
    input wire Cin,
    output wire S,
    output wire Cout);

    assign S = (A ^ B) ^ Cin;
    assign Cout = ((A ^ B) & Cin) | (A & B);

endmodule

module adder_9bit(
    input wire [8:0] A,
    input wire [8:0] B,
    input wire Cin,
    output wire [8:0] Sum,
    output wire Cout);

    wire C_add0;
    wire C_add1;
    wire C_add2;
    wire C_add3;
    wire C_add4;
    wire C_add5;
    wire C_add6;
    wire C_add7;

    adder_1bit add0(
        .A(A[0])
        .B(B[0])
        .Cin(Cin)
        .S(Sum[0])
        .Cout(C_add0));

    adder_1bit add1(
        .A(A[0])
        .B(B[0])
        .Cin(C_add0)
        .S(Sum[0])
        .Cout(C_add1));
        
    adder_1bit add2(
        .A(A[0])
        .B(B[0])
        .Cin(C_add1)
        .S(Sum[0])
        .Cout(C_add2));
        
    adder_1bit add3(
        .A(A[0])
        .B(B[0])
        .Cin(C_add2)
        .S(Sum[0])
        .Cout(C_add3));
        
    adder_1bit add4(
        .A(A[0])
        .B(B[0])
        .Cin(C_add3)
        .S(Sum[0])
        .Cout(C_add4));
        
    adder_1bit add5(
        .A(A[0])
        .B(B[0])
        .Cin(C_add4)
        .S(Sum[0])
        .Cout(C_add5));
        
    adder_1bit add6(
        .A(A[0])
        .B(B[0])
        .Cin(C_add5)
        .S(Sum[0])
        .Cout(C_add6));
        
    adder_1bit add7(
        .A(A[0])
        .B(B[0])
        .Cin(C_add6)
        .S(Sum[0])
        .Cout(C_add7));
        
    adder_1bit add8(
        .A(A[0])
        .B(B[0])
        .Cin(C_add7)
        .S(Sum[0])
        .Cout(Cout));

endmodule

module and_1bit(
    input wire A,
    input wire B,
    output wire C);

    assign C = A & B;

endmodule

module and_9bit(
    input wire [8:0] A,
    input wire [8:0] B,
    output wire [8:0] C);

    and_1bit and0(
        .A(A[0])
        .B(B[0])
        .C(C[0]));

    and_1bit and1(
        .A(A[1])
        .B(B[1])
        .C(C[1]));
        
    and_1bit and2(
        .A(A[2])
        .B(B[2])
        .C(C[2]));
        
    and_1bit and3(
        .A(A[3])
        .B(B[3])
        .C(C[3]));
        
    and_1bit and4(
        .A(A[4])
        .B(B[4])
        .C(C[4]));
    
    and_1bit and5(
        .A(A[5])
        .B(B[5])
        .C(C[5]));
        
    and_1bit and6(
        .A(A[6])
        .B(B[6])
        .C(C[6]));
        
    and_1bit and7(
        .A(A[7])
        .B(B[7])
        .C(C[7]));
        
    and_1bit and8(
        .A(A[8])
        .B(B[8])
        .C(C[8]));

endmodule

module gen_clock();

    reg clk;
    
    initial begin
        clk = 1'b0;
    end
    
    always begin
        #5 clk = ~clk; // Period to be determined
    end

endmodule

module mux_4_1(input wire [1:0] switch,
           input wire [8:0] A,B,C,D,
           output reg [8:0] out);
           
    always @(A,B,C,D,switch) begin
        case (switch)
            2'b00 : out = A;
            2'b01 : out = B;
            2'b10 : out = C;
            default: out = D;
        endcase
    end

endmodule

module not_1bit(
    input wire A,
    output wire B);
    
    assign B = ~A;

endmodule

module not_9bit(
    input wire [8:0] A,
    output wire [8:0] B);

    not_1bit not0(
        .A(A[0])
        .B(B[0]));

    not_1bit not1(
        .A(A[1])
        .B(B[1]));
        
    not_1bit not2(
        .A(A[2])
        .B(B[2]));
        
    not_1bit not3(
        .A(A[3])
        .B(B[3]));
        
    not_1bit not4(
        .A(A[4])
        .B(B[4]));
        
    not_1bit not5(
        .A(A[5])
        .B(B[5]));
        
    not_1bit not6(
        .A(A[6])
        .B(B[6]));
        
    not_1bit not7(
        .A(A[7])
        .B(B[7]));
        
    not_1bit not8(
        .A(A[8])
        .B(B[8]));

endmodule

module register(input wire clk, reset,
                input wire [1:0] En,
                input wire [8:0] Din,
                output reg [8:0] Dout);
                
    always @(posedge clk) begin
        if (reset == 1'b1) begin
            Dout <= 9'b000000000;
        end
        else if (En == 2'b00) begin
            Dout <= Din;
        end
        else begin
            Dout <= "ZZZZZZZZZ";
        end
    end

endmodule