Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date         : Fri Feb 15 12:32:11 2019
| Host         : DESKTOP-CSFKQTV running 64-bit major release  (build 9200)
| Command      : report_methodology -file RegFile_methodology_drc_routed.rpt -pb RegFile_methodology_drc_routed.pb -rpx RegFile_methodology_drc_routed.rpx
| Design       : RegFile
| Device       : xc7k160tifbg484-2L
| Speed File   : -2L
| Design State : Fully Routed
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Report Methodology

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Max violations: <unlimited>
             Violations found: 0
+------+----------+-------------+------------+
| Rule | Severity | Description | Violations |
+------+----------+-------------+------------+
+------+----------+-------------+------------+

2. REPORT DETAILS
-----------------