`timescale 1ns / 1ps

module ALU(
    input wire [2:0] opcode,
    input wire [8:0] operand0,
    input wire [8:0] operand1,
    output wire [8:0] result 
    );
    
    // Wires for connecting the modules to the mux
    wire [8:0] A,B,C,D,E,F,G,H;
    
    // A (000) - Add
    // B (001) - Subtract
    // C (010) - OR
    // D (011) - NOR
    // E (100) - AND
    // F (101) - Shift Logical Left
    // G (110) - Shift Logical Right
    // H (111)
    
    
    // MUX chooses which result to show based on the OPCODE
    mux_8_1 mux_result(
        .switch(opcode),
        .A(A),
        .B(B),
        .C(C),
        .D(D),
        .E(E),
        .F(F),
        .G(G),
        .H(H),
        .out(result));

endmodule