Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date             : Thu Apr 11 19:42:15 2019
| Host             : DESKTOP-8QFGS52 running 64-bit major release  (build 9200)
| Command          : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
| Design           : CPU9bits
| Device           : xc7k160tifbg484-2L
| Design State     : routed
| Grade            : industrial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 11.381       |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 11.237       |
| Device Static (W)        | 0.144        |
| Effective TJA (C/W)      | 2.5          |
| Max Ambient (C)          | 71.8         |
| Junction Temperature (C) | 53.2         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Slice Logic              |     1.762 |      175 |       --- |             --- |
|   LUT as Logic           |     1.689 |       83 |    101400 |            0.08 |
|   Register               |     0.045 |       61 |    202800 |            0.03 |
|   LUT as Distributed RAM |     0.020 |        9 |     35000 |            0.03 |
|   BUFG                   |     0.005 |        1 |        32 |            3.13 |
|   F7/F8 Muxes            |     0.003 |        1 |    101400 |           <0.01 |
|   Others                 |     0.000 |        7 |       --- |             --- |
| Signals                  |     1.630 |      143 |       --- |             --- |
| I/O                      |     7.846 |       12 |       285 |            4.21 |
| Static Power             |     0.144 |          |           |                 |
| Total                    |    11.381 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       0.950 |     3.650 |       3.574 |      0.075 |
| Vccaux    |       1.800 |     0.662 |       0.642 |      0.020 |
| Vcco33    |       3.300 |     0.000 |       0.000 |      0.000 |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
| Vcco18    |       1.800 |     3.716 |       3.715 |      0.001 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       0.950 |     0.002 |       0.000 |      0.002 |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccadc    |       1.800 |     0.018 |       0.000 |      0.018 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                             |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                                    |
| Clock nodes activity        | Low        | User specified less than 75% of clocks                 | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view           |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views         |
| Device models               | High       | Device models are Production                           |                                                                                                                    |
|                             |            |                                                        |                                                                                                                    |
| Overall confidence level    | Low        |                                                        |                                                                                                                    |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 2.5                      |
| Airflow (LFM)         | 250                      |
| Heat Sink             | medium (Medium Profile)  |
| ThetaSA (C/W)         | 4.2                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+


2.2 Clock Constraints
---------------------

+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+--------------------------+-----------+
| Name                     | Power (W) |
+--------------------------+-----------+
| CPU9bits                 |    11.237 |
|   EM                     |     0.071 |
|     dM                   |     0.071 |
|       memory_reg_0_1_0_0 |     0.002 |
|       memory_reg_0_1_1_1 |     0.002 |
|       memory_reg_0_1_2_2 |     0.002 |
|       memory_reg_0_1_3_3 |     0.002 |
|       memory_reg_0_1_4_4 |     0.002 |
|       memory_reg_0_1_5_5 |     0.002 |
|       memory_reg_0_1_6_6 |     0.002 |
|       memory_reg_0_1_7_7 |     0.002 |
|       memory_reg_0_1_8_8 |     0.002 |
|   FD                     |     2.780 |
|     FetchU               |     2.642 |
|       PC                 |     2.642 |
|     RF                   |     0.138 |
|       r0                 |     0.059 |
|       r1                 |     0.079 |
|   pipe1                  |     0.093 |
|   pipe2                  |     0.430 |
+--------------------------+-----------+