376 lines
10 KiB
Verilog
376 lines
10 KiB
Verilog
`timescale 1ns / 1ps
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module ControlUnit(
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input wire [3:0] instIn,
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input wire functBit,
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output reg [3:0] aluOut,
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output reg [2:0] FU,
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output reg [1:0] bank,
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output reg addi, mem, dataMemEn, RegEn, halt, link, js, compare0, compare1
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);
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always @(instIn, functBit)
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begin
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case(instIn)
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4'b0000: // Halt/NOP
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begin
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halt <= functBit;
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RegEn <= 1'b1;
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FU <= 3'b001; // Disable Branching
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addi <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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aluOut <= 4'b0000;
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mem <= 1'b0;
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b0;
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compare1 <= 1'b0;
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end
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4'b0001: // Load Byte
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begin
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aluOut <= 4'b0000;
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mem <= 1'b1;
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dataMemEn <= 1'b0; // Disabled
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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addi <= 1'b0;
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halt <= 1'b0;
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b1;
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end
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4'b0010: // Store Byte
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begin
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aluOut <= 4'b0000;
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mem <= 1'b0;
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dataMemEn <= 1'b1; // Enabled
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RegEn <= 1'b1;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b1;
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end
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4'b0011: // Link
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begin
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halt <= 1'b0;
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RegEn <= 1'b0;
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FU <= 3'b001;
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addi <= 1'b0;
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aluOut <= 4'b0000;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b1;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b0;
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compare1 <= 1'b0;
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end
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4'b0100: // Zero
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begin
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aluOut <= 4'b1011;
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b0;
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compare1 <= 1'b0;
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end
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4'b0101: // Add/Subtract
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if(functBit == 1) // Subtract
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begin
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aluOut <= 4'b0001;
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RegEn <= 1'b0;
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FU <= 3'b001;
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b1;
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end
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else // Add
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begin
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aluOut <= 4'b0000;
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b1;
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end
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4'b0110: // Add Immediate
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begin
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aluOut <= 4'b1010;
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addi <= 1'b1;
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b0;
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end
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4'b0111: // Set if Less Than
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begin
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aluOut <= 4'b1001;
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b1;
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end
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4'b1000: // Jump to Register
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begin
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aluOut <= 4'b0000;
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FU <= 3'b000;
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RegEn <= 1'b1;
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b0;
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end
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4'b1001: // Jump Forward
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begin
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aluOut <= 4'b0000;
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FU <= 3'b010;
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RegEn <= 1'b1;
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b0;
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compare1 <= 1'b0;
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end
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4'b1010: // Bank Load/Bank Store
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begin
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halt <= 1'b0;
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RegEn <= !functBit;
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FU <= 3'b001; // Disable Branching
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addi <= 1'b0;
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aluOut <= 4'b0000;
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dataMemEn <= 1'b0; // Disabled
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mem <= 1'b0;
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link <= 1'b0;
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bank <= {functBit,functBit};
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b0;
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end
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4'b1011: // Jump Backward
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begin
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aluOut <= 4'b0000;
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FU <= 3'b010;
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RegEn <= 1'b1;
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b1;
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compare0 <= 1'b0;
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compare1 <= 1'b0;
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end
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4'b1100: // Branch if Zero
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begin
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aluOut <= 4'b1010;
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FU <= 3'b110;
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RegEn <= 1'b1;
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b0;
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end
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4'b1101: // NOR
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begin
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aluOut <= 4'b0011;
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b1;
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end
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4'b1110: // OR/AND
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if(functBit == 1) // AND
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begin
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aluOut <= 4'b0100;
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b1;
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end
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else // OR
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begin
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aluOut <= 4'b0010;
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b1;
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end
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4'b1111: // Shift Right Logical/Shift Left Logical
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if(functBit == 1) // Shift Right Logical
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begin
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aluOut <= 4'b0110;
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b1;
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end
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else // Shift Left Logical
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begin
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aluOut <= 4'b0101;
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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dataMemEn <= 1'b0; // Disabled
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b1;
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compare1 <= 1'b1;
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end
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default:
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begin
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halt <= 1'b1;
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RegEn <= 1'b1;
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FU <= 3'b001;
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dataMemEn <= 1'b0; // Disabled
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addi <= 1'b0;
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aluOut <= 4'b0000;
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mem <= 1'b0;
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link <= 1'b0;
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bank <= 2'b10;
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js <= 1'b0;
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compare0 <= 1'b0;
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compare1 <= 1'b0;
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end
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endcase
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end
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endmodule
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module ControlUnit_tb();
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reg [3:0] instruction;
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reg functionB;
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wire [3:0] aluOutput;
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wire [2:0] FetchUnit;
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wire addImmediate, memory, RegEnable;
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ControlUnit ControlUnit0(
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.instIn(instruction),
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.functBit(functionB),
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.aluOut(aluOutput),
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.FU(FetchUnit),
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.addi(addImmediate),
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.mem(memory),
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.RegEn(RegEnable)
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);
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initial begin
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functionB = 1'b0;
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instruction = 4'b0101;
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#5
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functionB = 1'b1;
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#5
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functionB = 1'b0;
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instruction = 4'b1110;
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#5
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functionB = 1'b1;
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#5
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functionB = 1'b0;
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instruction = 4'b1111;
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#5
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functionB = 1'b1;
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#5
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instruction = 4'b0111;
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#5
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instruction = 4'b0110;
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#5
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instruction = 4'b1001;
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#5
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instruction = 4'b1100;
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#5
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instruction = 4'b1000;
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#5
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instruction = 4'b0001;
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#5
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instruction = 4'b0010;
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#5
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$finish;
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end
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endmodule
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