140 lines
2.9 KiB
Verilog
140 lines
2.9 KiB
Verilog
`timescale 1ns / 1ps
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module ALU(
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input wire [3:0] opcode, // NOT the same as the instruction set opcode
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input wire [8:0] operand0,
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input wire [8:0] operand1,
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output wire [8:0] result
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);
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// Wires for connecting the modules to the mux
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wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P;
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wire cout;
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// A (0000) - Add
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add_9bit add0(
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.A(operand0),
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.B(operand1),
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.Cin(1'b0),
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.Sum(result_A),
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.Cout(cout));
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// B (0001) - Subtract
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sub_9bit sub0(
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.A(operand0),
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.B(operand1),
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.C(result_B));
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// C (0010) - OR
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or_9bit or0(
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.A(operand0),
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.B(operand1),
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.C(result_C));
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// D (0011) - NOR
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nor_9bit nor0(
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.A(operand0),
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.B(operand1),
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.C(result_D));
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// E (0100) - AND
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and_9bit and0(
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.A(operand0),
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.B(operand1),
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.C(result_E));
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// F (0101) - Shift Left
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shift_left sl(
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.A(operand0),
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.B(result_F));
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// G (0110) - Shift Right Logical
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shift_right_logical srl(
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.A(operand0),
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.B(result_G));
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// H (0111) - Shift Right Arithmetic
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shift_right_arithmetic sra(
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.A(operand0),
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.B(result_H));
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// I (1000) - NOT
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not_9bit not0(
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.A(operand0),
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.B(result_I));
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// J (1001) - Less Than
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less_than less0(
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.A(operand0),
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.B(operand1),
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.C(result_J));
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// K (1010) - Zero
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BEQ zero0(
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.A(operand0),
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.B(result_K));
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// L (1011)
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// M (1100)
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// N (1101)
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// O (1110)
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// P (1111)
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// MUX chooses which result to show based on the ALU's opcode
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mux_16_1 mux0(
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.switch(opcode),
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.A(result_A),
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.B(result_B),
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.C(result_C),
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.D(result_D),
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.E(result_E),
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.F(result_F),
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.G(result_G),
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.H(result_H),
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.I(result_I),
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.J(result_J),
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.K(result_K),
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.L(result_L),
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.M(result_M),
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.N(result_N),
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.O(result_O),
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.P(result_P),
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.out(result));
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endmodule
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//testbench
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module alu_tb();
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reg [8:0] a;
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reg [8:0] b;
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reg [3:0] c;
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wire [8:0] d;
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ALU alu0(
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.operand0(a),
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.operand1(b),
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.opcode(c),
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.result(d));
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initial begin
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a = 9'b000000111;
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b = 9'b000111000;
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c = 4'b0000;
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#5
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a = 9'b000011000;
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b = 9'b000011000;
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c = 4'b0001;
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#5
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a = 9'b101010100;
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b = 9'b010101011;
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c = 4'b0010;
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#5
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a = 9'b101010100;
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b = 9'b010101000;
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c = 4'b0011;
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#5
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a = 9'b000110000;
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b = 9'b000111000;
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c = 4'b0100;
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#5
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a = 9'b01011000;
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c = 4'b0101;
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#5
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a = 9'b00001010;
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c = 4'b0110;
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#5
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$finish;
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end
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endmodule
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