145 lines
2.9 KiB
Verilog
145 lines
2.9 KiB
Verilog
`timescale 1ns / 1ps
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module RegFile(input wire clk, reset, enable,
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input wire [1:0] write_index, op0_idx, op1_idx,
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input wire [8:0] write_data,
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output wire [8:0] op0, op1);
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wire [3:0] decOut;
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wire [8:0] r0_out, r1_out, r2_out, r3_out;
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// To select a register En input must be 2'b00
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decoder d0(
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.en(enable),
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.index(write_index),
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.regOut(decOut)
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);
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register r0(
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.clk(clk),
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.reset(reset),
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.En(decOut[0]),
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.Din(write_data),
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.Dout(r0_out));
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register r1(
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.clk(clk),
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.reset(reset),
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.En(decOut[1]),
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.Din(write_data),
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.Dout(r1_out));
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register r2(
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.clk(clk),
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.reset(reset),
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.En(decOut[2]),
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.Din(write_data),
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.Dout(r2_out));
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register r3(
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.clk(clk),
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.reset(reset),
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.En(decOut[3]),
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.Din(write_data),
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.Dout(r3_out));
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mux_4_1 m0(
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.A(r0_out),
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.B(r1_out),
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.C(r2_out),
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.D(r3_out),
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.out(op0),
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.switch(op0_idx));
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mux_4_1 m1(
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.A(r0_out),
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.B(r1_out),
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.C(r2_out),
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.D(r3_out),
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.out(op1),
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.switch(op1_idx));
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endmodule
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//testbench
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module regFile_tb();
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reg [8:0] write_d;
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reg [1:0] w_idx, op0_idx, op1_idx;
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reg reset,clk, enable;
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wire [8:0] op0,op1;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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RegFile regFile0(
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.clk(clk),
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.enable(enable),
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.reset(reset),
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.write_index(w_idx),
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.op0_idx(op0_idx),
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.op1_idx(op1_idx),
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.write_data(write_d),
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.op0(op0),
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.op1(op1));
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initial begin
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reset = 0;
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#5
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reset = 1;
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#5
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reset = 0;
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enable = 1;
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w_idx = 2'b00;
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op0_idx = 2'b00;
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op1_idx = 2'b00;
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write_d = 9'b000000011;
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#5
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w_idx = 2'b01;
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#5
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w_idx = 2'b10;
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#5
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w_idx = 2'b11;
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#5
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reset = 0;
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w_idx = 2'b00;
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op0_idx = 2'b10;
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op1_idx = 2'b11;
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write_d = 9'b001111000;
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#5
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reset = 0;
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w_idx = 2'b01;
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op0_idx = 2'b00;
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op1_idx = 2'b01;
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write_d = 9'b000001111;
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#5
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reset = 0;
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w_idx = 2'b10;
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op0_idx = 2'b00;
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op1_idx = 2'b10;
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write_d = 9'b111000001;
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#5
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reset = 0;
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w_idx = 2'b11;
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op0_idx = 2'b11;
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op1_idx = 2'b10;
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write_d = 9'b100110001;
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#5
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reset = 1;
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w_idx = 2'b00;
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#5
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w_idx = 2'b10;
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#5
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w_idx = 2'b01;
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#5
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w_idx = 2'b11;
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#5
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$finish;
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end
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endmodule |