219 lines
4.6 KiB
Verilog
219 lines
4.6 KiB
Verilog
`timescale 1ns / 1ps
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module CPU9bits(
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input wire reset, clk,
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output wire done
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);
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wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP,jumpNeg;
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wire [2:0] FU;
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wire [3:0] aluOp;
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wire [1:0] bankS;
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wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js, dataMemEn;
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instructionMemory iM(
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.clk(clk),
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.address(PCout),
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.readData(instr)
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);
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dataMemory dM(
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.clk(clk),
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.writeEnable(dataMemEn),
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.writeData(op0),
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.address(op1),
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.readData(dataMemOut)
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);
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RegFile RF(
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.clk(clk),
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.reset(reset),
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.enable(RegEn),
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.write_index(instr[4:3]),
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.op0_idx(instr[4:3]),
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.op1_idx(instr[2:1]),
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.write_data(RFIn),
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.op0(op0),
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.op1(op1)
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);
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RegFile Bank(
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.clk(clk),
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.reset(reset),
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.enable(bankS[1]),
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.write_index(instr[2:1]),
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.op0_idx(instr[2:1]),
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.op1_idx(2'b00),//Doesn't matter
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.write_data(op0),
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.op0(bankOP),
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.op1()
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);
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FetchUnit FetchU(
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.clk(clk),
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.reset(reset),
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.op_idx(fetchBranch),
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.AddrIn(FUAddr),
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.AddrOut(PCout)
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);
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ALU alu(
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.opcode(aluOp),
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.operand0(op0),
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.operand1(op1),
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.result(AluOut)
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);
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ControlUnit CU(
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.instIn(instr[8:5]),
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.functBit(instr[0]),
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.aluOut(aluOp),
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.FU(FU),
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.addi(addiS),
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.mem(loadS),
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.dataMemEn(dataMemEn),
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.RegEn(RegEn),
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.halt(done),
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.link(link),
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.bank(bankS),
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.js(js)
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);
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//-----------------------Fetch Unit Stuff
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add_9bit JBAdder(
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.A(PCout),
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.B(JBRes),
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.Cin(1'b0),
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.Sum(FUJB),
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.Cout(cout0));
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mux_2_1 mux0(
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.A(op0),
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.B(FUJB),
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.out(FUAddr),
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.switch(FU[1]));
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twos_compliment_9bit two_comp0(
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.A({4'b0000,instr[4:0]}),
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.B(jumpNeg));
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mux_2_1 mux1(
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.A({4'b0000,instr[4:0]}),
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.B(jumpNeg),
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.out(SE2N),
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.switch(js));
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mux_2_1 mux2(
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.A(SE2N), //Jump -- Change with signer module!
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.B(SE1N),//Branch -- Change with signer module!
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.out(JBRes),
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.switch(FU[2]));
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sign_extend_3bit SE1(
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.A(instr[2:0]),
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.B(SE1N));
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bit1_mux_2_1 BranMux( // BEQ MUX
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.A(FU[0]),
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.B(AluOut[0]),
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.out(fetchBranch),
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.switch(FU[2])); // FU[2] only goes high when BEQ
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///--------------------------Addi Stuff
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add_9bit Addier(
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.A(SE3N), // Change with signer module!
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.B(op0),
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.Cin(1'b0),
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.Sum(AddiOut),
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.Cout(cout1));
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sign_extend_3bit SE3(
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.A(instr[2:0]),
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.B(SE3N));
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mux_2_1 mux3(
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.A(AluOut),
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.B(AddiOut),
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.out(loadMux),
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.switch(addiS));
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///--------------------------Mem stuff
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mux_2_1 mux4(
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.A(linkData),
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.B(dataMemOut), // This is DATA MEM
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.out(bankData),
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.switch(loadS));
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///--------------------------Bank stuff
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mux_2_1 mux5(
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.A(bankData),
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.B(bankOP),
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.out(RFIn),
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.switch(bankS[0]));
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///--------------------------Link Stuff
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mux_2_1 mux6(
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.A(loadMux),
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.B(PCout),
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.out(linkData),
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.switch(link));
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endmodule
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module CPU9bits_tb();
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reg clk, reset;
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wire done;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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CPU9bits CPU9bits0(
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.reset(reset),
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.clk(clk),
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.done(done));
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initial begin
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#10
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reset = 1'b1;
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#10
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reset = 1'b0;
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#850
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// instruction = 9'b000100000;
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// reset = 1'b1;
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// #10
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// reset = 1'b0;
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// #10
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// instruction = 9'b000101000;
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// #10
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// instruction = 9'b010100010;
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// #10
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// instruction = 9'b111100000;
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// #10
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// instruction = 9'b111100000;
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// #10
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// instruction = 9'b001101000;
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// #10
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// instruction = 9'b010001000;
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// #10
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// instruction = 9'b000000000;
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// #10
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$finish;
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end
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endmodule |