185 lines
4.2 KiB
Verilog
185 lines
4.2 KiB
Verilog
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|
// --------------------------------------------------------------------------------
|
|
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
|
// Date : Fri Feb 15 12:36:16 2019
|
|
// Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
|
// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file {C:/Users/JoseIgnacio/CA
|
|
// Lab/lab2CA.sim/sim_1/impl/timing/xsim/RegFile_time_impl.v}
|
|
// Design : RegFile
|
|
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
|
|
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
|
|
// Device : xc7k160tifbg484-2L
|
|
// --------------------------------------------------------------------------------
|
|
`timescale 1 ps / 1 ps
|
|
`define XIL_TIMING
|
|
|
|
(* ECO_CHECKSUM = "2b285f13" *)
|
|
(* NotValidForBitStream *)
|
|
module RegFile
|
|
(clk,
|
|
reset,
|
|
write_index,
|
|
op0_idx,
|
|
op1_idx,
|
|
write_data,
|
|
op0,
|
|
op1);
|
|
input clk;
|
|
input reset;
|
|
input [1:0]write_index;
|
|
input [1:0]op0_idx;
|
|
input [1:0]op1_idx;
|
|
input [8:0]write_data;
|
|
output [8:0]op0;
|
|
output [8:0]op1;
|
|
|
|
wire [8:0]op0;
|
|
wire [8:0]op1;
|
|
|
|
initial begin
|
|
$sdf_annotate("RegFile_time_impl.sdf",,,,"tool_control");
|
|
end
|
|
OBUFT \op0_OBUF[0]_inst
|
|
(.I(1'b0),
|
|
.O(op0[0]),
|
|
.T(1'b1));
|
|
OBUFT \op0_OBUF[1]_inst
|
|
(.I(1'b0),
|
|
.O(op0[1]),
|
|
.T(1'b1));
|
|
OBUFT \op0_OBUF[2]_inst
|
|
(.I(1'b0),
|
|
.O(op0[2]),
|
|
.T(1'b1));
|
|
OBUFT \op0_OBUF[3]_inst
|
|
(.I(1'b0),
|
|
.O(op0[3]),
|
|
.T(1'b1));
|
|
OBUFT \op0_OBUF[4]_inst
|
|
(.I(1'b0),
|
|
.O(op0[4]),
|
|
.T(1'b1));
|
|
OBUFT \op0_OBUF[5]_inst
|
|
(.I(1'b0),
|
|
.O(op0[5]),
|
|
.T(1'b1));
|
|
OBUFT \op0_OBUF[6]_inst
|
|
(.I(1'b0),
|
|
.O(op0[6]),
|
|
.T(1'b1));
|
|
OBUFT \op0_OBUF[7]_inst
|
|
(.I(1'b0),
|
|
.O(op0[7]),
|
|
.T(1'b1));
|
|
OBUFT \op0_OBUF[8]_inst
|
|
(.I(1'b0),
|
|
.O(op0[8]),
|
|
.T(1'b1));
|
|
OBUFT \op1_OBUF[0]_inst
|
|
(.I(1'b0),
|
|
.O(op1[0]),
|
|
.T(1'b1));
|
|
OBUFT \op1_OBUF[1]_inst
|
|
(.I(1'b0),
|
|
.O(op1[1]),
|
|
.T(1'b1));
|
|
OBUFT \op1_OBUF[2]_inst
|
|
(.I(1'b0),
|
|
.O(op1[2]),
|
|
.T(1'b1));
|
|
OBUFT \op1_OBUF[3]_inst
|
|
(.I(1'b0),
|
|
.O(op1[3]),
|
|
.T(1'b1));
|
|
OBUFT \op1_OBUF[4]_inst
|
|
(.I(1'b0),
|
|
.O(op1[4]),
|
|
.T(1'b1));
|
|
OBUFT \op1_OBUF[5]_inst
|
|
(.I(1'b0),
|
|
.O(op1[5]),
|
|
.T(1'b1));
|
|
OBUFT \op1_OBUF[6]_inst
|
|
(.I(1'b0),
|
|
.O(op1[6]),
|
|
.T(1'b1));
|
|
OBUFT \op1_OBUF[7]_inst
|
|
(.I(1'b0),
|
|
.O(op1[7]),
|
|
.T(1'b1));
|
|
OBUFT \op1_OBUF[8]_inst
|
|
(.I(1'b0),
|
|
.O(op1[8]),
|
|
.T(1'b1));
|
|
endmodule
|
|
`ifndef GLBL
|
|
`define GLBL
|
|
`timescale 1 ps / 1 ps
|
|
|
|
module glbl ();
|
|
|
|
parameter ROC_WIDTH = 100000;
|
|
parameter TOC_WIDTH = 0;
|
|
|
|
//-------- STARTUP Globals --------------
|
|
wire GSR;
|
|
wire GTS;
|
|
wire GWE;
|
|
wire PRLD;
|
|
tri1 p_up_tmp;
|
|
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
|
|
|
wire PROGB_GLBL;
|
|
wire CCLKO_GLBL;
|
|
wire FCSBO_GLBL;
|
|
wire [3:0] DO_GLBL;
|
|
wire [3:0] DI_GLBL;
|
|
|
|
reg GSR_int;
|
|
reg GTS_int;
|
|
reg PRLD_int;
|
|
|
|
//-------- JTAG Globals --------------
|
|
wire JTAG_TDO_GLBL;
|
|
wire JTAG_TCK_GLBL;
|
|
wire JTAG_TDI_GLBL;
|
|
wire JTAG_TMS_GLBL;
|
|
wire JTAG_TRST_GLBL;
|
|
|
|
reg JTAG_CAPTURE_GLBL;
|
|
reg JTAG_RESET_GLBL;
|
|
reg JTAG_SHIFT_GLBL;
|
|
reg JTAG_UPDATE_GLBL;
|
|
reg JTAG_RUNTEST_GLBL;
|
|
|
|
reg JTAG_SEL1_GLBL = 0;
|
|
reg JTAG_SEL2_GLBL = 0 ;
|
|
reg JTAG_SEL3_GLBL = 0;
|
|
reg JTAG_SEL4_GLBL = 0;
|
|
|
|
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
|
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
|
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
|
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
|
|
|
assign (strong1, weak0) GSR = GSR_int;
|
|
assign (strong1, weak0) GTS = GTS_int;
|
|
assign (weak1, weak0) PRLD = PRLD_int;
|
|
|
|
initial begin
|
|
GSR_int = 1'b1;
|
|
PRLD_int = 1'b1;
|
|
#(ROC_WIDTH)
|
|
GSR_int = 1'b0;
|
|
PRLD_int = 1'b0;
|
|
end
|
|
|
|
initial begin
|
|
GTS_int = 1'b1;
|
|
#(TOC_WIDTH)
|
|
GTS_int = 1'b0;
|
|
end
|
|
|
|
endmodule
|
|
`endif
|