142 lines
2.9 KiB
Verilog
142 lines
2.9 KiB
Verilog
`timescale 1ns / 1ps
|
|
|
|
module CPU9bits(input wire [8:0] instr,
|
|
input wire reset, clk,
|
|
output wire done,
|
|
output wire [8:0] reg0
|
|
);
|
|
|
|
wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
|
|
wire [2:0] FU;
|
|
wire [3:0] aluOp;
|
|
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1;
|
|
|
|
RegFile RF(
|
|
.clk(clk),
|
|
.reset(reset),
|
|
.enable(RegEn),
|
|
.write_index(instr[4:3]),
|
|
.op0_idx(instr[4:3]),
|
|
.op1_idx(instr[2:1]),
|
|
.write_data(RFIn),
|
|
.op0(op0),
|
|
.op1(op1)
|
|
);
|
|
|
|
FetchUnit FetchU(
|
|
.clk(clk),
|
|
.reset(reset),
|
|
.op_idx(fetchBranch),
|
|
.AddrIn(FUAddr),
|
|
.AddrOut(PCout)
|
|
);
|
|
|
|
ALU alu(
|
|
.opcode(aluOp),
|
|
.operand0(op0),
|
|
.operand1(op1),
|
|
.result(AluOut)
|
|
);
|
|
|
|
ControlUnit CU(
|
|
.instIn(instr[8:5]),
|
|
.functBit(instr[0]),
|
|
.aluOut(aluOp),
|
|
.FU(FU),
|
|
.addi(addiS),
|
|
.mem(loadS),
|
|
.RegEn(RegEn),
|
|
.halt(done)
|
|
);
|
|
|
|
|
|
//-----------------------Fetch Unit Stuff
|
|
|
|
add_9bit JBAdder(
|
|
.A(PCout),
|
|
.B(JBRes),
|
|
.Cin(1'b0),
|
|
.Sum(FUJB),
|
|
.Cout(cout0));
|
|
|
|
mux_2_1 mux1(
|
|
.A(op1),
|
|
.B(FUJB),
|
|
.out(FUAddr),
|
|
.switch(FU[1]));
|
|
|
|
mux_2_1 mux2(
|
|
.A({4'b0000,instr[4:0]}), //Jump
|
|
.B({6'b000000,instr[2:0]}),//Branch
|
|
.out(JBRes),
|
|
.switch(FU[2]));
|
|
|
|
bit1_mux_2_1 BranMux( // BEQ MUX
|
|
.A(FU[0]),
|
|
.B(op1[0]),
|
|
.out(fetchBranch),
|
|
.switch(FU[2])); // FU[2] only goes high when BEQ
|
|
|
|
///--------------------------Addi Stuff
|
|
|
|
add_9bit Addier(
|
|
.A({6'b000000,instr[2:0]}),
|
|
.B(op1),
|
|
.Cin(1'b0),
|
|
.Sum(AddiOut),
|
|
.Cout(cout1));
|
|
|
|
mux_2_1 mux3(
|
|
.A(AluOut),
|
|
.B(AddiOut),
|
|
.out(loadMux),
|
|
.switch(addiS));
|
|
|
|
mux_2_1 mux4(
|
|
.A(loadMux),
|
|
.B(9'b000000001),
|
|
.out(RFIn),
|
|
.switch(loadS));
|
|
|
|
|
|
endmodule
|
|
|
|
module CPU9bits_tb();
|
|
reg [8:0] instruction;
|
|
reg clk, reset;
|
|
wire done;
|
|
|
|
initial begin
|
|
clk = 1'b0;
|
|
end
|
|
always begin
|
|
#5 clk = ~clk; // Period to be determined
|
|
end
|
|
|
|
CPU9bits CPU9bits0(
|
|
.instr(instruction),
|
|
.reset(reset),
|
|
.clk(clk),
|
|
.done(done));
|
|
|
|
initial begin
|
|
reset = 1'b1;
|
|
#10
|
|
reset = 1'b0;
|
|
#10
|
|
instruction = 9'b000100000;
|
|
#10
|
|
instruction = 9'b000101000;
|
|
#10
|
|
instruction = 9'b010100010;
|
|
#10
|
|
instruction = 9'b111100000;
|
|
#10
|
|
instruction = 9'b111100000;
|
|
#10
|
|
instruction = 9'b000000000;
|
|
#10
|
|
$finish;
|
|
|
|
end
|
|
endmodule |