WilliamMiceli 32faa621d6 Added Two's Compliment module

2019-02-15 17:18:54 -05:00

..

ALU.v

Renamed some things; adder is now implemented in ALU

2019-02-15 17:09:44 -05:00

BasicModules.v

Added Two's Compliment module

2019-02-15 17:18:54 -05:00

fetchFile.v

fetch unit

2019-02-15 11:20:14 -05:00

FetchUnit.v

Modularized project; mux, clock, and reg done; Progress on RegFile

2019-02-15 12:24:26 -05:00

lab2testing.v

Modularized project; mux, clock, and reg done; Progress on RegFile

2019-02-15 12:24:26 -05:00

RegFile.v

Added outputs to the MUXes for the registers

2019-02-15 17:01:43 -05:00