76 lines
1.5 KiB
Verilog
76 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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module lab2testing();
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endmodule
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module regFile(input wire clk, reset,
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input wire [1:0] write_index, op0_idx, op1_idx,
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input wire [8:0] write_data,
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output wire [8:0] op0, op1);
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wire [8:0] r0_out, r1_out, r2_out, r3_out;
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register r0(
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.clk(clk),
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.reset(reset),
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.En({write_index[0], write_index[1]}),
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.Din(write_data),
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.Dout(r0_out));
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register r1(
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.clk(clk),
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.reset(reset),
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.En({write_index[0], ~write_index[1]}),
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.Din(write_data),
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.Dout(r1_out));
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register r2(
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.clk(clk),
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.reset(reset),
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.En({~write_index[0], write_index[1]}),
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.Din(write_data),
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.Dout(r2_out));
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register r3(
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.clk(clk),
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.reset(reset),
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.En({~write_index[0], ~write_index[1]}),
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.Din(write_data),
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.Dout(r3_out));
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Mux m0(
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.A(r0_out),
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.B(r1_out),
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.C(r2_out),
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.D(r3_out),
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.switch(op0_idx));
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Mux m1(
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.A(r0_out),
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.B(r1_out),
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.C(r2_out),
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.D(r3_out),
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.switch(op1_idx));
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endmodule
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module register(input wire clk, reset,
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input wire [1:0] En,
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input wire [8:0] Din,
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output reg [8:0] Dout);
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endmodule
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module MUX();
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endmodule
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module fetchUnit(input wire clk,
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input wire [8:0] AddrIn,
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output wire [8:0] AddrOut);
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endmodule
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