60 lines
1.1 KiB
Verilog
60 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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module BasicModules();
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endmodule
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module gen_clock();
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reg clk;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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endmodule
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module register(input wire clk, reset,
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input wire [1:0] En,
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input wire [8:0] Din,
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output reg [8:0] Dout);
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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Dout <= 9'b000000000;
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end
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else if (En == 2'b00) begin
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Dout <= Din;
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end
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else begin
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Dout <= "ZZZZZZZZZ";
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end
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end
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endmodule
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module mux(input wire [1:0] switch,
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input wire [8:0] A,B,C,D,
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output reg [8:0] out);
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always @(A,B,C,D,switch) begin
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if (switch == 2'b00) begin
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out = A;
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end
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else if (switch == 2'b01) begin
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out = B;
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end
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else if (switch == 2'b11) begin
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out = C;
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end
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else begin
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out = D;
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end
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end
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endmodule
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