69 lines
1.2 KiB
Verilog
69 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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module adder_1bit(
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input wire A,
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input wire B,
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input wire Cin,
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output wire S,
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output wire Cout);
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assign S = (A ^ B) ^ Cin;
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assign Cout = ((A ^ B) & Cin) | (A & B);
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endmodule
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module gen_clock();
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reg clk;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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endmodule
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module inverter(
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input wire A,
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output wire B);
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assign B = ~A;
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endmodule
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module mux(input wire [1:0] switch,
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input wire [8:0] A,B,C,D,
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output reg [8:0] out);
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always @(A,B,C,D,switch) begin
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case (switch)
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2'b00 : out = A;
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2'b01 : out = B;
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2'b10 : out = C;
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default: out = D;
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endcase
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end
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endmodule
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module register(input wire clk, reset,
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input wire [1:0] En,
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input wire [8:0] Din,
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output reg [8:0] Dout);
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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Dout <= 9'b000000000;
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end
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else if (En == 2'b00) begin
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Dout <= Din;
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end
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else begin
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Dout <= "ZZZZZZZZZ";
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end
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end
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endmodule |