WilliamMiceli 456fcf0804 Few renames; added left and right shifts, possibly some other stuff

2019-02-15 17:50:30 -05:00

..

ALU.v

Comments and slight renames

2019-02-15 17:49:12 -05:00

BasicModules.v

Few renames; added left and right shifts, possibly some other stuff

2019-02-15 17:50:30 -05:00

fetchFile.v

fetch unit

2019-02-15 11:20:14 -05:00

FetchUnit.v

Modularized project; mux, clock, and reg done; Progress on RegFile

2019-02-15 12:24:26 -05:00

lab2testing.v

Modularized project; mux, clock, and reg done; Progress on RegFile

2019-02-15 12:24:26 -05:00

RegFile.v

Added outputs to the MUXes for the registers

2019-02-15 17:01:43 -05:00