42 lines
988 B
Verilog
42 lines
988 B
Verilog
`timescale 1ns / 1ps
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module ALU(
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input wire [2:0] opcode, // NOT the same as the instruction set opcode
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input wire [8:0] operand0,
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input wire [8:0] operand1,
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output wire [8:0] result
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);
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// Wires for connecting the modules to the mux
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wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H;
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// A (000) - Add
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adder_9bit(
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.A(operand0),
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.B(operand1),
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.Cin(1'b0),
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.Sum(result_A));
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// B (001) - Subtract
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// C (010) - OR
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// D (011) - NOR
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// E (100) - AND
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// F (101) - Shift Logical Left
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// G (110) - Shift Logical Right
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// H (111)
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// MUX chooses which result to show based on the ALU's opcode
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mux_8_1 mux0(
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.switch(opcode),
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.A(result_A),
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.B(result_B),
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.C(result_C),
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.D(result_D),
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.E(result_E),
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.F(result_F),
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.G(result_G),
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.H(result_H),
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.out(result));
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endmodule
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