41 lines
719 B
Verilog
41 lines
719 B
Verilog
`timescale 1ns / 1ps
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module ALU(
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input wire [8:0] instruction,
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output wire [8:0] result
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);
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// Wires for connecting the modules to the mux
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wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P;
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// Please place modules in order of OPCODE, to make them easier to find
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// MUX chooses which result to show based on the OPCODE
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mux_16_1 mux_result(
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.switch(instruction[8:5]),
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.A(A),
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.B(B),
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.C(C),
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.D(D),
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.E(E),
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.F(F),
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.G(G),
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.H(H),
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.I(I),
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.J(J),
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.K(K),
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.L(L),
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.M(M),
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.N(N),
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.O(O),
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.P(P),
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.out(result));
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endmodule
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