50 lines
2.3 KiB
Plaintext
50 lines
2.3 KiB
Plaintext
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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| Date : Sun Mar 24 18:39:15 2019
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| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
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| Command : report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx
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| Design : CPU9bits_tb
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| Device : xc7k160tifbg484-2L
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| Speed File : -2L
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| Design State : Fully Routed
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Report DRC
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: design_1
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Design limits: <entire design considered>
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Ruledeck: default
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Max violations: <unlimited>
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Violations found: 1
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+----------+----------+-----------------------------------------------------+------------+
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| Rule | Severity | Description | Violations |
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+----------+----------+-----------------------------------------------------+------------+
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| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
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+----------+----------+-----------------------------------------------------+------------+
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2. REPORT DETAILS
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-----------------
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CFGBVS-1#1 Warning
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Missing CFGBVS and CONFIG_VOLTAGE Design Properties
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Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
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set_property CFGBVS value1 [current_design]
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#where value1 is either VCCO or GND
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set_property CONFIG_VOLTAGE value2 [current_design]
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#where value2 is the voltage provided to configuration bank 0
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Refer to the device configuration user guide for more information.
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Related violations: <none>
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