185 lines
7.2 KiB
Plaintext
185 lines
7.2 KiB
Plaintext
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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| Date : Sat Apr 6 14:01:18 2019
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| Host : WM-G75VW running 64-bit major release (build 9200)
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| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
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| Design : CPU9bits
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| Device : 7k160tifbg484-2L
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| Design State : Synthesized
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Utilization Design Information
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Table of Contents
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-----------------
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1. Slice Logic
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1.1 Summary of Registers by Type
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2. Memory
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3. DSP
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4. IO and GT Specific
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5. Clocking
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6. Specific Feature
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7. Primitives
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8. Black Boxes
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9. Instantiated Netlists
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1. Slice Logic
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--------------
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+-------------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------------------+------+-------+-----------+-------+
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| Slice LUTs* | 193 | 0 | 101400 | 0.19 |
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| LUT as Logic | 193 | 0 | 101400 | 0.19 |
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| LUT as Memory | 0 | 0 | 35000 | 0.00 |
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| Slice Registers | 81 | 0 | 202800 | 0.04 |
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| Register as Flip Flop | 81 | 0 | 202800 | 0.04 |
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| Register as Latch | 0 | 0 | 202800 | 0.00 |
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| F7 Muxes | 11 | 0 | 50700 | 0.02 |
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| F8 Muxes | 0 | 0 | 25350 | 0.00 |
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+-------------------------+------+-------+-----------+-------+
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* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
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1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0 | _ | - | - |
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| 0 | _ | - | Set |
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| 0 | _ | - | Reset |
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| 0 | _ | Set | - |
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| 0 | _ | Reset | - |
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| 0 | Yes | - | - |
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| 0 | Yes | - | Set |
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| 0 | Yes | - | Reset |
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| 0 | Yes | Set | - |
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| 81 | Yes | Reset | - |
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+-------+--------------+-------------+--------------+
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2. Memory
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---------
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+-------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------------+------+-------+-----------+-------+
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| Block RAM Tile | 0.5 | 0 | 325 | 0.15 |
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| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
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| RAMB18 | 1 | 0 | 650 | 0.15 |
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| RAMB18E1 only | 1 | | | |
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+-------------------+------+-------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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3. DSP
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------
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+-----------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------+------+-------+-----------+-------+
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| DSPs | 0 | 0 | 600 | 0.00 |
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+-----------+------+-------+-----------+-------+
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4. IO and GT Specific
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---------------------
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+-----------------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------------------------+------+-------+-----------+-------+
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| Bonded IOB | 12 | 0 | 285 | 4.21 |
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| Bonded IPADs | 0 | 0 | 14 | 0.00 |
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| Bonded OPADs | 0 | 0 | 8 | 0.00 |
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| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
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| PHASER_REF | 0 | 0 | 8 | 0.00 |
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| OUT_FIFO | 0 | 0 | 32 | 0.00 |
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| IN_FIFO | 0 | 0 | 32 | 0.00 |
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| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
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| IBUFDS | 0 | 0 | 275 | 0.00 |
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| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
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| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 |
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| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
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| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
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| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
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| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
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| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
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| ILOGIC | 0 | 0 | 285 | 0.00 |
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| OLOGIC | 0 | 0 | 285 | 0.00 |
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+-----------------------------+------+-------+-----------+-------+
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5. Clocking
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-----------
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+------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+------------+------+-------+-----------+-------+
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| BUFGCTRL | 1 | 0 | 32 | 3.13 |
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| BUFIO | 0 | 0 | 32 | 0.00 |
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| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
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| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
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| BUFMRCE | 0 | 0 | 16 | 0.00 |
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| BUFHCE | 0 | 0 | 120 | 0.00 |
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| BUFR | 0 | 0 | 32 | 0.00 |
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+------------+------+-------+-----------+-------+
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6. Specific Feature
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-------------------
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+-------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------+------+-------+-----------+-------+
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| BSCANE2 | 0 | 0 | 4 | 0.00 |
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| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
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| DNA_PORT | 0 | 0 | 1 | 0.00 |
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| EFUSE_USR | 0 | 0 | 1 | 0.00 |
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| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
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| ICAPE2 | 0 | 0 | 2 | 0.00 |
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| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
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| STARTUPE2 | 0 | 0 | 1 | 0.00 |
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| XADC | 0 | 0 | 1 | 0.00 |
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+-------------+------+-------+-----------+-------+
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7. Primitives
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-------------
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+----------+------+---------------------+
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| Ref Name | Used | Functional Category |
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+----------+------+---------------------+
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| LUT6 | 135 | LUT |
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| FDRE | 81 | Flop & Latch |
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| LUT5 | 33 | LUT |
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| LUT4 | 23 | LUT |
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| LUT3 | 21 | LUT |
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| LUT2 | 13 | LUT |
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| MUXF7 | 11 | MuxFx |
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| OBUF | 10 | IO |
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| IBUF | 2 | IO |
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| RAMB18E1 | 1 | Block Memory |
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| BUFG | 1 | Clock |
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+----------+------+---------------------+
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8. Black Boxes
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--------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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9. Instantiated Netlists
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------------------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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