92 lines
1.5 KiB
Verilog
92 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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module FetchUnit(input wire clk, reset,
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input wire [1:0] op_idx,
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input wire [8:0] AddrIn,
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output wire [8:0] AddrOut);
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//Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a)
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wire [8:0] progC_out, result_a, result_m;
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register PC(
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.clk(clk),
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.reset(reset),
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.En(2'b00),
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.Din(result_m),
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.Dout(progC_out));
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//Adds 1 to the program counter
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add_9bit PCAdder(
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.A(progC_out),
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.B(9'b000000001),
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.Cin(9'b000000000),
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.Sum(AddrOut));
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mux_2_1 PCmux(
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.A(AddrIn),
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.B(AddrOut),
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.out(result_m),
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.switch(op_idx));
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endmodule
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//testbench
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module fetchUnit_tb();
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reg [8:0] addr_in;
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reg opidx;
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reg reset;
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wire [8:0] addr_out;
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reg clk;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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FetchUnit fetchUnit0(
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.clk(clk),
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.reset(reset),
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.op_idx(opidx),
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.AddrIn(addr_in),
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.AddrOut(addr_out));
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initial begin
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reset = 0;
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opidx = 1'b1;
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addr_in = 0'b000000000;
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#5
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reset = 1;
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#5
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reset = 0;
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opidx = 1'b0;
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addr_in = 9'b000001111;
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#5
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#5
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addr_in = 9'b011000011;
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#5
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#5
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opidx = 1'b1;
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#5
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#5
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#5
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#5
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opidx = 1'b0;
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addr_in = 9'b000001111;
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#5
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#5
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addr_in = 9'b010010011;
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#5
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opidx = 1'b1;
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#5
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#5
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#5
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#5
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#5
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$finish;
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end
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endmodule |