211 lines
3.5 KiB
Verilog
211 lines
3.5 KiB
Verilog
`timescale 1ns / 1ps
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module adder_1bit(
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input wire A,
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input wire B,
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input wire Cin,
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output wire S,
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output wire Cout);
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assign S = (A ^ B) ^ Cin;
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assign Cout = ((A ^ B) & Cin) | (A & B);
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endmodule
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module adder_9bit(
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input wire [8:0] A,
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input wire [8:0] B,
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input wire Cin,
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output wire [8:0] Sum,
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output wire Cout);
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wire C_add0;
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wire C_add1;
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wire C_add2;
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wire C_add3;
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wire C_add4;
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wire C_add5;
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wire C_add6;
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wire C_add7;
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adder_1bit add0(
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.A(A[0])
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.B(B[0])
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.Cin(Cin)
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.S(Sum[0])
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.Cout(C_add0));
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adder_1bit add1(
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.A(A[0])
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.B(B[0])
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.Cin(C_add0)
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.S(Sum[0])
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.Cout(C_add1));
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adder_1bit add2(
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.A(A[0])
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.B(B[0])
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.Cin(C_add1)
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.S(Sum[0])
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.Cout(C_add2));
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adder_1bit add3(
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.A(A[0])
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.B(B[0])
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.Cin(C_add2)
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.S(Sum[0])
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.Cout(C_add3));
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adder_1bit add4(
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.A(A[0])
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.B(B[0])
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.Cin(C_add3)
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.S(Sum[0])
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.Cout(C_add4));
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adder_1bit add5(
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.A(A[0])
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.B(B[0])
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.Cin(C_add4)
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.S(Sum[0])
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.Cout(C_add5));
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adder_1bit add6(
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.A(A[0])
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.B(B[0])
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.Cin(C_add5)
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.S(Sum[0])
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.Cout(C_add6));
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adder_1bit add7(
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.A(A[0])
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.B(B[0])
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.Cin(C_add6)
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.S(Sum[0])
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.Cout(C_add7));
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adder_1bit add8(
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.A(A[0])
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.B(B[0])
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.Cin(C_add7)
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.S(Sum[0])
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.Cout(Cout));
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endmodule
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module and_1bit(
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input wire A,
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input wire B,
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output wire C);
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assign C = A & B;
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endmodule
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module and_9bit(
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input wire [8:0] A,
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input wire [8:0] B,
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output wire [8:0] C);
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and_1bit and0(
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.A(A[0])
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.B(B[0])
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.C(C[0]));
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and_1bit and1(
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.A(A[1])
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.B(B[1])
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.C(C[1]));
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and_1bit and2(
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.A(A[2])
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.B(B[2])
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.C(C[2]));
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and_1bit and3(
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.A(A[3])
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.B(B[3])
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.C(C[3]));
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and_1bit and4(
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.A(A[4])
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.B(B[4])
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.C(C[4]));
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and_1bit and5(
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.A(A[5])
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.B(B[5])
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.C(C[5]));
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and_1bit and6(
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.A(A[6])
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.B(B[6])
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.C(C[6]));
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and_1bit and7(
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.A(A[7])
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.B(B[7])
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.C(C[7]));
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and_1bit and8(
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.A(A[8])
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.B(B[8])
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.C(C[8]));
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endmodule
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module gen_clock();
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reg clk;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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endmodule
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module inverter(
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input wire A,
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output wire B);
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assign B = ~A;
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endmodule
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module mux_4_1(input wire [1:0] switch,
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input wire [8:0] A,B,C,D,
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output reg [8:0] out);
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always @(A,B,C,D,switch) begin
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case (switch)
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2'b00 : out = A;
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2'b01 : out = B;
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2'b10 : out = C;
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default: out = D;
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endcase
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end
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endmodule
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module register(input wire clk, reset,
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input wire [1:0] En,
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input wire [8:0] Din,
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output reg [8:0] Dout);
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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Dout <= 9'b000000000;
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end
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else if (En == 2'b00) begin
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Dout <= Din;
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end
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else begin
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Dout <= "ZZZZZZZZZ";
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end
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end
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endmodule |