239 lines
9.2 KiB
Verilog
239 lines
9.2 KiB
Verilog
`timescale 1ns / 1ps
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module instructionMemory(
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input wire clk,
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input wire [8:0] address,
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output reg [8:0] readData
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);
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reg [8:0] memory [512:0];
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initial begin
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//Equation Solver
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// memory[0] <= 9'b000000000;
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// memory[1] <= 9'b000100000; //load
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// memory[2] <= 9'b000101000; //load
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// memory[3] <= 9'b010100010; //add
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// memory[4] <= 9'b111100000; //shift left
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// memory[5] <= 9'b111100000; //shift left
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// //Testing all instructions
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// memory[6] <= 9'b010100011; //sub
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// memory[7] <= 9'b011001011; //addi
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// memory[8] <= 9'b011110000; //slt
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// memory[9] <= 9'b110111000; //nor
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// memory[10] <= 9'b111011000; //or
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// memory[11] <= 9'b111011001; //and
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// memory[12] <= 9'b111111000; //sll
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// memory[13] <= 9'b111111001; //srl
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// // memory[14] <= 9'b100100010; //j
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// memory[14] <= 9'b010001000; //zero
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// memory[15] <= 9'b110001001; //beq
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// memory[16] <= 9'b100001000; //jr
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// memory[17] <= 9'b100111100; //j
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//String Compare
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// memory[0] <= 9'b000000000;
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// memory[1] <= 9'b010000000;
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// memory[2] <= 9'b010001000;
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// memory[3] <= 9'b010010000;
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// memory[4] <= 9'b010011000;
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// memory[5] <= 9'b000100000;
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// memory[6] <= 9'b011001001;
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// memory[7] <= 9'b000101010;
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// memory[8] <= 9'b011010010;
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// memory[9] <= 9'b000110100;
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// memory[10] <= 9'b011011011;
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// memory[11] <= 9'b000111110;
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// memory[12] <= 9'b101010000;
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// memory[13] <= 9'b101000010;
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// memory[14] <= 9'b101001100;
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// memory[15] <= 9'b101011110; //ends initialization
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// memory[16] <= 9'b101000011;
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// memory[17] <= 9'b101001101;
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// memory[18] <= 9'b000110000;
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// memory[19] <= 9'b000111010;
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// memory[20] <= 9'b110010001;
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// memory[21] <= 9'b100100001;
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// memory[22] <= 9'b100110000;
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// memory[23] <= 9'b110011001;
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// memory[24] <= 9'b100100001;
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// memory[25] <= 9'b100101101;
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// memory[26] <= 9'b011000001;
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// memory[27] <= 9'b011001001;
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// memory[28] <= 9'b101000010;
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// memory[29] <= 9'b101001100;
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// memory[30] <= 9'b010110111;
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// memory[31] <= 9'b110010001;
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// memory[32] <= 9'b101110010;
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// memory[33] <= 9'b101000000;
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// memory[34] <= 9'b101001110;
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// memory[35] <= 9'b001001000;
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// memory[36] <= 9'b011000001;
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// memory[37] <= 9'b101000000;
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// memory[38] <= 9'b101111000;
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// memory[39] <= 9'b000000000;
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// Bubble Sort
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memory[0] <= 9'b000000001;
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memory[1] <= 9'b010000000;
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memory[2] <= 9'b000100000;
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memory[3] <= 9'b010001000;
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memory[4] <= 9'b010010000;
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memory[5] <= 9'b010011000;
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memory[6] <= 9'b101001000;
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memory[7] <= 9'b101001010;
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memory[8] <= 9'b100100011;
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memory[9] <= 9'b101001001;
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memory[10] <= 9'b011001001;
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memory[11] <= 9'b101001000;
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memory[12] <= 9'b101001001;
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memory[13] <= 9'b011101000;
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memory[14] <= 9'b110001010;
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memory[15] <= 9'b100100001;
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memory[16] <= 9'b100110100;
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memory[17] <= 9'b101001001;
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memory[18] <= 9'b011001001;
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memory[19] <= 9'b000110010;
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memory[20] <= 9'b011001001;
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memory[21] <= 9'b000111010;
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memory[22] <= 9'b101011110;
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memory[23] <= 9'b011111100;
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memory[24] <= 9'b110011010;
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memory[25] <= 9'b100100001;
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memory[26] <= 9'b101110010;
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memory[27] <= 9'b101001001;
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memory[28] <= 9'b011001001;
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memory[29] <= 9'b101011111;
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memory[30] <= 9'b001011010;
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memory[31] <= 9'b011001001;
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memory[32] <= 9'b001010010;
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memory[33] <= 9'b010001000;
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memory[34] <= 9'b011001001;
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memory[35] <= 9'b101001010;
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memory[36] <= 9'b101111100;
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memory[37] <= 9'b101001011;
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memory[38] <= 9'b110001001;
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memory[39] <= 9'b100100001;
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memory[40] <= 9'b100100011;
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memory[41] <= 9'b010001000;
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memory[42] <= 9'b101001000;
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memory[43] <= 9'b101111011;
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memory[44] <= 9'b000000000;
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// Binary Search
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// memory[0] <= 9'b000000000;
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// memory[1] <= 9'b000000000;
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// memory[2] <= 9'b000000000;
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// memory[3] <= 9'b000000000;
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// memory[4] <= 9'b000000000;
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// memory[5] <= 9'b000000000;
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// memory[6] <= 9'b011001011; //addi R1, 3 (N = 3)
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// memory[7] <= 9'b011001011; //addi R1, 3 (N = 3)
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// memory[8] <= 9'b011001011; //addi R1, 3 (N = 3)
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// memory[9] <= 9'b011001011; //addi R1, 3 (N = 3)
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// memory[10] <= 9'b011001011; //addi R1, 3 (N = 3)
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// memory[11] <= 9'b011010010; //addi R2, 2 (inputAddr = 2)
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// memory[12] <= 9'b000111110; //lb R3, R3
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// memory[13] <= 9'b101011010; //banks R3, 1
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// memory[14] <= 9'b011001011; //addi R1, 3 (N = 3)
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// memory[15] <= 9'b101000000; //loop: banks R0, 0
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// memory[16] <= 9'b011100010; //slt R0, R1
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// memory[17] <= 9'b110000001; //beq R0, Exit
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// memory[18] <= 9'b100100001; //j Skip0
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// memory[19] <= 9'b100101110; //Exit: j Loose
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// memory[20] <= 9'b010101000; //Skip0: add R2, R0
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// memory[21] <= 9'b010101010; //add R2, R1
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// memory[22] <= 9'b111110000; //sll R2
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// memory[23] <= 9'b101011011; //bankl R3,1
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// memory[24] <= 9'b010111100; //add R3, R2
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// memory[25] <= 9'b101001100; //banks R1, 2
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// memory[26] <= 9'b000100110; //lb R0, R3
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// memory[27] <= 9'b010001000; //zero R1
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// memory[28] <= 9'b011001010; //addi R1, 1 (numAddr = 1)
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// memory[29] <= 9'b000101010; //lb R1, R1
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// memory[30] <= 9'b100100001; //j SkipU
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// memory[31] <= 9'b101110001; //j TransLoop
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// memory[32] <= 9'b101010110; //SkipU: banks R2, 3
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// memory[33] <= 9'b100100001; //j SkipD
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// memory[34] <= 9'b100110111; //j TransLoose
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// memory[35] <= 9'b010010000; //SkipD: zero R2
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// memory[36] <= 9'b010110010; //add R2, R1
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// memory[37] <= 9'b010101001; //sub R1, R0
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// memory[38] <= 9'b110001001; //beq R1, Go1
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// memory[39] <= 9'b100100001; //j Skip1
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// memory[40] <= 9'b100101001; //Go1: j Win
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// memory[41] <= 9'b010001000; //Skip1: zero R1
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// memory[42] <= 9'b010101100; //add R1, R2
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// memory[43] <= 9'b011100010; //slt R0, R1
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// memory[44] <= 9'b110001001; //beq R1, Go2
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// memory[45] <= 9'b100100110; //j Skip2
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// memory[46] <= 9'b010000000; //Go2: zero R0
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// memory[47] <= 9'b011000010; //addi R0, 1
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// memory[48] <= 9'b101001111; //bankl R1,3
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// memory[49] <= 9'b010100010; //add R0, R1
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// memory[50] <= 9'b101001101; //bankl R1,2
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// memory[51] <= 9'b101110101; //j loop
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// memory[52] <= 9'b010001000; //Skip2: zero R1
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// memory[53] <= 9'b011001111; //addi R1, -1
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// memory[54] <= 9'b101000111; //bankl R0, 3
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// memory[55] <= 9'b010101000; //add R1, R0
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// memory[56] <= 9'b101000001; //bankl R0,0
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// memory[57] <= 9'b101111011; //j loop
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// memory[58] <= 9'b010000000; //Loose: zero R0
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// memory[59] <= 9'b011000111; //addi R0, -1
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// memory[60] <= 9'b101000110; //banks R0, 3
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// memory[61] <= 9'b100100000; //j Win
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// memory[62] <= 9'b000000000; //Win: halt
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end
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always@(address)begin
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readData <= memory[address];
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end
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endmodule
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module instructionMemory_tb();
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reg clk;
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reg [8:0] address;
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wire [8:0] readData;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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instructionMemory iM0(
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.clk(clk),
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.address(address),
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.readData(readData)
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);
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initial begin
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#10
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address = 9'b000000000;
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#5
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address = 9'b000000001;
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#5
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address = 9'b000000010;
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#5
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address = 9'b000000011;
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#5
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address = 9'b000000100;
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#5
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address = 9'b000000101;
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#5
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address = 9'b000000111;
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#5
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$finish;
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end
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endmodule |