61 lines
2.2 KiB
Plaintext
61 lines
2.2 KiB
Plaintext
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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| Date : Sun Mar 24 12:14:36 2019
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| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
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| Command : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
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| Design : CPU9bits
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| Device : xc7k160tifbg484-2L
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| Speed File : -2L
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| Design State : Fully Routed
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Report Methodology
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: design_1
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Design limits: <entire design considered>
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Max violations: <unlimited>
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Violations found: 5
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+-----------+----------+-----------------------------+------------+
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| Rule | Severity | Description | Violations |
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+-----------+----------+-----------------------------+------------+
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| TIMING-17 | Warning | Non-clocked sequential cell | 5 |
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+-----------+----------+-----------------------------+------------+
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2. REPORT DETAILS
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-----------------
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TIMING-17#1 Warning
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Non-clocked sequential cell
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The clock pin FetchU/PC/Dout_reg[0]/C is not reached by a timing clock
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Related violations: <none>
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TIMING-17#2 Warning
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Non-clocked sequential cell
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The clock pin FetchU/PC/Dout_reg[1]/C is not reached by a timing clock
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Related violations: <none>
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TIMING-17#3 Warning
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Non-clocked sequential cell
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The clock pin FetchU/PC/Dout_reg[2]/C is not reached by a timing clock
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Related violations: <none>
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TIMING-17#4 Warning
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Non-clocked sequential cell
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The clock pin FetchU/PC/Dout_reg[3]/C is not reached by a timing clock
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Related violations: <none>
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TIMING-17#5 Warning
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Non-clocked sequential cell
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The clock pin FetchU/PC/Dout_reg[4]/C is not reached by a timing clock
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Related violations: <none>
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