jose.rodriguezlabra 94f0267a13 stuff

2019-03-24 14:16:03 -04:00

..

ALU.v

Added zeroing instr

2019-03-16 14:34:36 -04:00

BasicModules.v

Added zeroing instr

2019-03-16 14:34:36 -04:00

ControlUnit.v

stuff

2019-03-24 14:16:03 -04:00

CPU9bits.v

stuff

2019-03-24 14:16:03 -04:00

dataMemory.v

Added bank to CPU9bits

2019-03-24 12:11:12 -04:00

FetchUnit.v

Better Sim

2019-03-14 14:37:58 -04:00

instructionMemory.v

Added bank to CPU9bits

2019-03-24 12:11:12 -04:00

RegFile.v

Fixed bugs, finished BEQ, Added Halt

2019-03-13 11:14:52 -04:00