127 lines
4.9 KiB
XML
127 lines
4.9 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553093609">
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<File Type="PA-TCL" Name="CPU9bits.tcl"/>
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<File Type="BITSTR-BMM" Name="CPU9bits_bd.bmm"/>
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<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
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<File Type="OPT-DCP" Name="CPU9bits_opt.dcp"/>
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<File Type="OPT-HWDEF" Name="CPU9bits.hwdef"/>
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<File Type="PWROPT-DCP" Name="CPU9bits_pwropt.dcp"/>
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<File Type="PLACE-DCP" Name="CPU9bits_placed.dcp"/>
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<File Type="PLACE-PRE-SIMILARITY" Name="CPU9bits_incremental_reuse_pre_placed.rpt"/>
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<File Type="BG-BGN" Name="CPU9bits.bgn"/>
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<File Type="POSTPLACE-PWROPT-DCP" Name="CPU9bits_postplace_pwropt.dcp"/>
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<File Type="BG-BIN" Name="CPU9bits.bin"/>
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<File Type="PHYSOPT-DCP" Name="CPU9bits_physopt.dcp"/>
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<File Type="BITSTR-MSK" Name="CPU9bits.msk"/>
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<File Type="ROUTE-ERROR-DCP" Name="CPU9bits_routed_error.dcp"/>
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<File Type="ROUTE-DCP" Name="CPU9bits_routed.dcp"/>
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<File Type="ROUTE-BLACKBOX-DCP" Name="CPU9bits_routed_bb.dcp"/>
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<File Type="BITSTR-LTX" Name="CPU9bits.ltx"/>
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<File Type="BITSTR-MMI" Name="CPU9bits.mmi"/>
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<File Type="BITSTR-SYSDEF" Name="CPU9bits.sysdef"/>
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<File Type="ROUTE-TIMING-PB" Name="CPU9bits_timing_summary_routed.pb"/>
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<File Type="POSTROUTE-PHYSOPT-DCP" Name="CPU9bits_postroute_physopt.dcp"/>
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<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="CPU9bits_postroute_physopt_bb.dcp"/>
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<File Type="BG-BIT" Name="CPU9bits.bit"/>
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<File Type="BITSTR-RBT" Name="CPU9bits.rbt"/>
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<File Type="BITSTR-NKY" Name="CPU9bits.nky"/>
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<File Type="BG-DRC" Name="CPU9bits.drc"/>
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<File Type="RDI-RDI" Name="CPU9bits.vdi"/>
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<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
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<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sources_1/new/ALU.v">
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
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</File>
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<File Path="$PSRCDIR/sources_1/new/ControlUnit.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</File>
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<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
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</File>
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<File Path="$PSRCDIR/sources_1/new/RegFile.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="implementation"/>
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</File>
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<File Path="$PSRCDIR/sources_1/new/dataMemory.v">
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<File Path="$PSRCDIR/sources_1/new/instructionMemory.v">
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</File>
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<File Path="$PSRCDIR/sources_1/new/CPU9bits.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="CPU9bits"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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<Filter Type="Constrs"/>
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<Config>
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
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<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
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<Filter Type="Utils"/>
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<Config>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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</GenRun>
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