240 lines
7.2 KiB
Verilog
240 lines
7.2 KiB
Verilog
`timescale 1ns / 1ps
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module ControlUnit(
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input wire [3:0] instIn,
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input wire functBit,
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output reg [3:0] aluOut,
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output reg [2:0] FU,
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output reg addi,
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output reg mem,
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output reg RegEn,
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output reg halt,
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output reg link);
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always @(instIn, functBit)begin
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case(instIn)
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4'b0101:
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if(functBit == 1) begin
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aluOut <= 4'b0001; //sub
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RegEn <= 1'b0;
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FU <= 3'b001;
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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link <= 1'b0;
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end
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else begin
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aluOut <= 4'b0000; //Add
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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link <= 1'b0;
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end
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4'b1101: begin
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aluOut <= 4'b0011; //nor
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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link <= 1'b0;
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end
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4'b0100: begin
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aluOut <= 4'b1011; //zero
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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link <= 1'b0;
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end
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4'b1110:
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if(functBit == 1) begin
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aluOut <= 4'b0100; //and
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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link <= 1'b0;
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end
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else begin
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aluOut <= 4'b0010; //or
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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link <= 1'b0;
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end
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4'b1111:
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if(functBit == 1) begin
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aluOut <= 4'b0110; //srl
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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link <= 1'b0;
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end
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else begin
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aluOut <= 4'b0101; //shift left
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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link <= 1'b0;
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end
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4'b0111: begin
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aluOut <= 4'b1001; //Less than
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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link <= 1'b0;
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end
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4'b0110: begin
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aluOut <= 4'b0000;
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addi <= 1'b1; // addi
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RegEn <= 1'b1;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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mem <= 1'b0;
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link <= 1'b0;
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end
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4'b1001: begin
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aluOut <= 4'b0000;
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FU <= 3'b010; // jump
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RegEn <= 1'b1;
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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link <= 1'b0;
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end
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4'b0011: begin // link
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halt <= 1'b0;
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RegEn <= 1'b0;
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FU <= 3'b001;
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addi <= 1'b0;
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aluOut <= 4'b0000;
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mem <= 1'b0;
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link <= 1'b1;
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end
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4'b1100: begin
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aluOut <= 4'b0000;
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FU <= 3'b110; // branch
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RegEn <= 1'b1;
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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link <= 1'b0;
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end
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4'b1000: begin
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aluOut <= 4'b0000;
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FU <= 3'b000; // jumpreg
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RegEn <= 1'b1;
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halt <= 1'b0;
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addi <= 1'b0;
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mem <= 1'b0;
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link <= 1'b0;
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end
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4'b0001: begin
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aluOut <= 4'b0000;
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mem <= 1'b1; // load
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RegEn <= 1'b0;
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FU <= 3'b001; // Disable Branching
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addi <= 1'b0;
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halt <= 1'b0;
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link <= 1'b0;
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end
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4'b0010: begin
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aluOut <= 4'b0000;
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mem <= 1'b0; // store
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RegEn <= 1'b1;
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FU <= 3'b001; // Disable Branching
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halt <= 1'b0;
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addi <= 1'b0;
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link <= 1'b0;
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end
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4'b0000: begin // regs should initialize at 0, so we shouldn't need to declare it everywhere
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halt <= 1'b1; // halt
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RegEn <= 1'b1;
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FU <= 3'b001; // Disable Branching
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addi <= 1'b0;
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aluOut <= 4'b0000;
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mem <= 1'b0;
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link <= 1'b0;
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end
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default: begin
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halt <= 1'b1;
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RegEn <= 1'b1;
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FU <= 3'b001;
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addi <= 1'b0;
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aluOut <= 4'b0000;
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mem <= 1'b0;
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link <= 1'b0;
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end
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endcase
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end
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endmodule
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module ControlUnit_tb();
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reg [3:0] instruction;
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reg functionB;
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wire [3:0] aluOutput;
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wire [2:0] FetchUnit;
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wire addImmediate;
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wire memory;
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wire RegEnable;
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ControlUnit ControlUnit0(
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.instIn(instruction),
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.functBit(functionB),
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.aluOut(aluOutput),
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.FU(FetchUnit),
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.addi(addImmediate),
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.mem(memory),
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.RegEn(RegEnable)
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);
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initial begin
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functionB = 1'b0;
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instruction = 4'b0101;
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#5
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functionB = 1'b1;
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#5
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functionB = 1'b0;
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instruction = 4'b1110;
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#5
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functionB = 1'b1;
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#5
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functionB = 1'b0;
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instruction = 4'b1111;
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#5
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functionB = 1'b1;
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#5
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instruction = 4'b0111;
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#5
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instruction = 4'b0110;
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#5
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instruction = 4'b1001;
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#5
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instruction = 4'b1100;
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#5
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instruction = 4'b1000;
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#5
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instruction = 4'b0001;
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#5
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instruction = 4'b0010;
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#5
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$finish;
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end
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endmodule
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