85 lines
1.9 KiB
Verilog
85 lines
1.9 KiB
Verilog
`timescale 1ns / 1ps
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module instructionMemory(
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input wire clk,
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input wire [8:0] address,
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output reg [8:0] readData
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);
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reg [8:0] memory [512:0];
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initial begin
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//Equation Solver
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memory[0] <= 9'b000000000;
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memory[1] <= 9'b000100000; //load
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memory[2] <= 9'b000101000; //load
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memory[3] <= 9'b010100010; //add
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memory[4] <= 9'b111100000; //shift left
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memory[5] <= 9'b111100000; //shift left
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//Testing all instructions
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memory[6] <= 9'b010100011; //sub
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memory[7] <= 9'b011001011; //addi
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memory[8] <= 9'b011110000; //slt
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memory[9] <= 9'b110111000; //nor
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memory[10] <= 9'b111011000; //or
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memory[11] <= 9'b111011001; //and
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memory[12] <= 9'b111111000; //sll
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memory[13] <= 9'b111111001; //srl
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// memory[14] <= 9'b100100010; //j
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memory[14] <= 9'b010001000; //zero
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memory[15] <= 9'b110001101; //beq
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memory[16] <= 9'b100001000; //jr
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memory[17] <= 9'b100111100; //j
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end
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always@(address)begin
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readData <= memory[address];
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end
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endmodule
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module instructionMemory_tb();
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reg clk;
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reg [8:0] address;
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wire [8:0] readData;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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instructionMemory iM0(
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.clk(clk),
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.address(address),
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.readData(readData)
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);
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initial begin
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#10
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address = 9'b000000000;
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#5
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address = 9'b000000001;
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#5
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address = 9'b000000010;
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#5
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address = 9'b000000011;
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#5
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address = 9'b000000100;
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#5
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address = 9'b000000101;
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#5
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address = 9'b000000111;
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#5
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$finish;
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end
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endmodule |