89 lines
2.1 KiB
Verilog
89 lines
2.1 KiB
Verilog
`timescale 1ns / 1ps
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module dataMemory(
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input wire clk, writeEnable,
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input wire [8:0] address, writeData,
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output reg [8:0] readData
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);
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reg [8:0] memory [15:0];
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initial begin
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memory[0] <= 9'b000000000;
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memory[1] <= 9'b000000000;
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memory[2] <= 9'b000000000;
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memory[3] <= 9'b000000000;
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memory[4] <= 9'b000000000;
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memory[5] <= 9'b000000000;
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memory[6] <= 9'b000000000;
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memory[7] <= 9'b000000000;
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memory[8] <= 9'b000000000;
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memory[9] <= 9'b000000000;
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memory[10] <= 9'b000000000;
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memory[11] <= 9'b000000000;
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memory[12] <= 9'b000000000;
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memory[13] <= 9'b000000000;
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memory[14] <= 9'b000000000;
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memory[15] <= 9'b000000000;
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end
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always@(address, clk, memory)begin
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if(clk == 1'b1)begin
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readData <= memory[address];
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if(writeEnable == 1'b0)begin
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memory[address] <= writeData;
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end
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else begin
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memory[address] <= memory[address];
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end
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end
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end
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endmodule
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module dataMemory_tb();
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reg clk, writeEnable;
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reg [8:0] address, writeData;
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wire [8:0] readData;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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dataMemory dM0(
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.clk(clk),
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.writeEnable(writeEnable),
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.writeData(writeData),
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.address(address),
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.readData(readData)
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);
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initial begin
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writeEnable = 1'b0;
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address = 9'b000000000;
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writeData = 9'b010101010;
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#5
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address = 9'b000000100;
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writeData = 9'b010101010;
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#10
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writeEnable = 1'b1;
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address = 9'b000000000;
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writeData = 9'b010101010;
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#10
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address = 9'b000000001;
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writeData = 9'b000001111;
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#10
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address = 9'b000000010;
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writeData = 9'b000000101;
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#10
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address = 9'b000000011;
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writeData = 9'b000000011;
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#10
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address = 9'b00000010;
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writeData = 9'b000001101;
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#5
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$finish;
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end
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endmodule |