66 lines
1.5 KiB
Verilog
66 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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module FDModule(
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input wire reset, clk, FUIdx, En,
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input wire [8:0] RFIn, AddrIn,
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input wire[1:0] RFIdx,
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output wire [1:0] op0_idx, op1_idx,
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output wire [50:0] result,
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output wire done, compare0, compare1
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);
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wire [8:0] instr, op1, op0, PCout;
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wire [3:0] aluOp;
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wire [2:0] FU;
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wire [1:0] bankS;
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wire addiS, RegEn, loadS, halt, link, js, dataMemEn ;
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assign result = {instr,op0,op1,PCout,addiS,RegEn,loadS,link,js,dataMemEn,aluOp,FU,bankS}; // concat all signals into one
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assign op0_idx = instr[4:3];
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assign op1_idx = instr[2:1];
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instructionMemory iM(
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.address(PCout),
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.readData(instr)
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);
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FetchUnit FetchU(
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.clk(clk),
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.reset(reset),
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.op_idx(FUIdx),
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.AddrIn(AddrIn),
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.AddrOut(PCout)
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);
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RegFile RF(
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.clk(clk),
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.reset(reset),
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.write_index(RFIdx),
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.op0_idx(instr[4:3]),
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.op1_idx(instr[2:1]),
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.write_data(RFIn),
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.op0(op0),
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.op1(op1),
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.En(En)
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);
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ControlUnit CU(
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.instIn(instr[8:5]),
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.functBit(instr[0]),
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.aluOut(aluOp),
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.FU(FU),
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.addi(addiS),
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.mem(loadS),
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.dataMemEn(dataMemEn),
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.RegEn(RegEn),
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.halt(done),
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.link(link),
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.bank(bankS),
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.js(js),
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.compare0(compare0),
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.compare1(compare1)
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);
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endmodule
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