c85ad153dc
All of the instructions seem to be working other than beq. I might just be calling it wrong
495 lines
41 KiB
Plaintext
495 lines
41 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Wed Mar 20 10:53:36 2019
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# Process ID: 12136
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# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
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# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
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# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
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# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
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#-----------------------------------------------------------
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source CPU9bits.tcl -notrace
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Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 8176
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---------------------------------------------------------------------------------
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Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.945 ; gain = 102.359
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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WARNING: [Synth 8-567] referenced signal 'clk' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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WARNING: [Synth 8-567] referenced signal 'memory' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
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INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
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INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
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INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
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INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
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INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
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INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
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INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
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INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
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INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
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INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
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INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
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INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
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INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
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INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
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INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
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INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
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INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
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INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
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INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
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INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
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INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
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INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
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INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
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INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
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WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sign_extend_2bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:965]
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INFO: [Synth 8-6155] done synthesizing module 'sign_extend_2bit' (25#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:965]
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WARNING: [Synth 8-689] width (3) of port connection 'A' does not match port width (2) of module 'sign_extend_2bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:89]
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INFO: [Synth 8-6157] synthesizing module 'sign_extend_4bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1035]
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INFO: [Synth 8-6155] done synthesizing module 'sign_extend_4bit' (26#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1035]
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WARNING: [Synth 8-689] width (5) of port connection 'A' does not match port width (4) of module 'sign_extend_4bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:93]
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INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
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INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (27#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
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WARNING: [Synth 8-689] width (3) of port connection 'A' does not match port width (2) of module 'sign_extend_2bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:112]
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INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (28#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
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WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
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WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
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WARNING: [Synth 8-3331] design instructionMemory has unconnected port clk
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---------------------------------------------------------------------------------
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Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.844 ; gain = 158.258
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.844 ; gain = 158.258
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7k160tifbg484-2L
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.844 ; gain = 158.258
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---------------------------------------------------------------------------------
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INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
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INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
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INFO: [Synth 8-5546] ROM "memory_reg[15]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[14]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[13]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[12]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[11]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[10]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[9]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[8]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[7]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[6]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[5]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[4]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[3]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[2]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[1]" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "memory_reg[0]" won't be mapped to RAM because it is too sparse
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WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[15]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[14]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[13]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[12]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[11]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[10]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[9]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[8]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[7]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[6]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[5]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[4]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[3]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[2]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[1]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[0]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 446.785 ; gain = 189.199
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---------------------------------------------------------------------------------
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INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_2bit) to 'SE3'
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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No constraint files found.
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---------------------------------------------------------------------------------
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Start RTL Component Statistics
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---------------------------------------------------------------------------------
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Detailed RTL Component Info :
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+---XORs :
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2 Input 1 Bit XORs := 144
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+---Registers :
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9 Bit Registers := 5
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+---Muxes :
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7 Input 9 Bit Muxes := 1
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2 Input 9 Bit Muxes := 22
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4 Input 9 Bit Muxes := 2
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2 Input 4 Bit Muxes := 1
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4 Input 4 Bit Muxes := 1
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15 Input 4 Bit Muxes := 1
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2 Input 3 Bit Muxes := 2
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15 Input 3 Bit Muxes := 1
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16 Input 1 Bit Muxes := 16
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2 Input 1 Bit Muxes := 17
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3 Input 1 Bit Muxes := 16
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15 Input 1 Bit Muxes := 5
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---------------------------------------------------------------------------------
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Finished RTL Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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Hierarchical RTL Component report
|
|
Module instructionMemory
|
|
Detailed RTL Component Info :
|
|
+---Muxes :
|
|
7 Input 9 Bit Muxes := 1
|
|
Module dataMemory
|
|
Detailed RTL Component Info :
|
|
+---Muxes :
|
|
2 Input 9 Bit Muxes := 16
|
|
16 Input 1 Bit Muxes := 16
|
|
2 Input 1 Bit Muxes := 16
|
|
3 Input 1 Bit Muxes := 16
|
|
Module decoder
|
|
Detailed RTL Component Info :
|
|
+---Muxes :
|
|
2 Input 4 Bit Muxes := 1
|
|
4 Input 4 Bit Muxes := 1
|
|
Module register
|
|
Detailed RTL Component Info :
|
|
+---Registers :
|
|
9 Bit Registers := 1
|
|
Module mux_4_1
|
|
Detailed RTL Component Info :
|
|
+---Muxes :
|
|
4 Input 9 Bit Muxes := 1
|
|
Module add_1bit
|
|
Detailed RTL Component Info :
|
|
+---XORs :
|
|
2 Input 1 Bit XORs := 2
|
|
Module mux_2_1
|
|
Detailed RTL Component Info :
|
|
+---Muxes :
|
|
2 Input 9 Bit Muxes := 1
|
|
Module ControlUnit
|
|
Detailed RTL Component Info :
|
|
+---Muxes :
|
|
15 Input 4 Bit Muxes := 1
|
|
2 Input 3 Bit Muxes := 2
|
|
15 Input 3 Bit Muxes := 1
|
|
15 Input 1 Bit Muxes := 5
|
|
Module bit1_mux_2_1
|
|
Detailed RTL Component Info :
|
|
+---Muxes :
|
|
2 Input 1 Bit Muxes := 1
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Hierarchical Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
Part Resources:
|
|
DSPs: 600 (col length:100)
|
|
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
|
|
---------------------------------------------------------------------------------
|
|
Finished Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
No constraint files found.
|
|
---------------------------------------------------------------------------------
|
|
Start Cross Boundary and Area Optimization
|
|
---------------------------------------------------------------------------------
|
|
Warning: Parallel synthesis criteria is not met
|
|
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[8]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[7]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[6]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[5]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[4]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[3]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[2]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[1]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[0]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][8]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][7]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][6]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][5]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][4]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][3]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][2]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][1]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][0]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][8]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][7]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][6]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][5]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][4]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][3]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][2]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][1]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][0]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][8]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][7]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][6]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][5]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][4]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][3]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][2]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][1]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][0]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][8]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][7]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][6]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][5]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][4]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][3]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][2]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][1]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][0]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][8]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][7]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][6]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][5]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][4]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][3]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][2]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][1]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][0]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][8]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][7]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][6]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][5]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][4]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][3]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][2]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][1]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][0]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][8]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][7]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][6]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][5]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][4]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][3]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][2]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][1]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][0]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][8]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][7]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][6]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][5]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][4]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][3]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][2]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][1]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][0]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][8]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][7]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][6]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][5]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][4]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][3]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][2]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][1]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][0]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][8]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][7]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][6]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][5]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][4]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][3]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][2]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][1]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][0]) is unused and will be removed from module CPU9bits.
|
|
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[5][8]) is unused and will be removed from module CPU9bits.
|
|
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
---------------------------------------------------------------------------------
|
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 594.980 ; gain = 337.395
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
No constraint files found.
|
|
---------------------------------------------------------------------------------
|
|
Start Timing Optimization
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 594.980 ; gain = 337.395
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start Technology Mapping
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 594.980 ; gain = 337.395
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report Check Netlist:
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
| |Item |Errors |Warnings |Status |Description |
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Instances
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start Rebuilding User Hierarchy
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Ports
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Handling Custom Attributes
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Nets
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Writing Synthesis Report
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report BlackBoxes:
|
|
+-+--------------+----------+
|
|
| |BlackBox name |Instances |
|
|
+-+--------------+----------+
|
|
+-+--------------+----------+
|
|
|
|
Report Cell Usage:
|
|
+------+-----+------+
|
|
| |Cell |Count |
|
|
+------+-----+------+
|
|
|1 |BUFG | 1|
|
|
|2 |LUT2 | 1|
|
|
|3 |LUT3 | 2|
|
|
|4 |LUT4 | 1|
|
|
|5 |FDRE | 3|
|
|
|6 |IBUF | 2|
|
|
|7 |OBUF | 1|
|
|
+------+-----+------+
|
|
|
|
Report Instance Areas:
|
|
+------+---------+----------+------+
|
|
| |Instance |Module |Cells |
|
|
+------+---------+----------+------+
|
|
|1 |top | | 11|
|
|
|2 | FetchU |FetchUnit | 7|
|
|
|3 | PC |register | 7|
|
|
+------+---------+----------+------+
|
|
---------------------------------------------------------------------------------
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
|
---------------------------------------------------------------------------------
|
|
Synthesis finished with 0 errors, 0 critical warnings and 185 warnings.
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.789 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
No Unisim elements were transformed.
|
|
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
|
87 Infos, 132 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
synth_design completed successfully
|
|
synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 681.789 ; gain = 431.723
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.789 ; gain = 0.000
|
|
WARNING: [Constraints 18-5210] No constraints selected for write.
|
|
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
|
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
|
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
|
INFO: [Common 17-206] Exiting Vivado at Wed Mar 20 10:54:03 2019...
|