28 lines
606 B
Verilog
28 lines
606 B
Verilog
`timescale 1ns / 1ps
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
// Company:
|
|
// Engineer:
|
|
//
|
|
// Create Date: 02/15/2019 12:19:52 PM
|
|
// Design Name:
|
|
// Module Name: FetchUnit
|
|
// Project Name:
|
|
// Target Devices:
|
|
// Tool Versions:
|
|
// Description:
|
|
//
|
|
// Dependencies:
|
|
//
|
|
// Revision:
|
|
// Revision 0.01 - File Created
|
|
// Additional Comments:
|
|
//
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
module FetchUnit(input wire clk,
|
|
input wire [8:0] AddrIn,
|
|
output wire [8:0] AddrOut);
|
|
|
|
endmodule
|