cb91f6656a
I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
93 lines
3.8 KiB
XML
93 lines
3.8 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550680547">
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<File Type="BITSTR-BMM" Name="FetchUnit_bd.bmm"/>
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<File Type="PA-TCL" Name="FetchUnit.tcl"/>
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<File Type="OPT-DCP" Name="FetchUnit_opt.dcp"/>
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<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
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<File Type="OPT-HWDEF" Name="FetchUnit.hwdef"/>
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<File Type="BG-BGN" Name="FetchUnit.bgn"/>
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<File Type="PWROPT-DCP" Name="FetchUnit_pwropt.dcp"/>
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<File Type="PLACE-DCP" Name="FetchUnit_placed.dcp"/>
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<File Type="PLACE-PRE-SIMILARITY" Name="FetchUnit_incremental_reuse_pre_placed.rpt"/>
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<File Type="POSTPLACE-PWROPT-DCP" Name="FetchUnit_postplace_pwropt.dcp"/>
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<File Type="BG-BIN" Name="FetchUnit.bin"/>
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<File Type="PHYSOPT-DCP" Name="FetchUnit_physopt.dcp"/>
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<File Type="BITSTR-MSK" Name="FetchUnit.msk"/>
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<File Type="ROUTE-ERROR-DCP" Name="FetchUnit_routed_error.dcp"/>
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<File Type="ROUTE-DCP" Name="FetchUnit_routed.dcp"/>
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<File Type="ROUTE-BLACKBOX-DCP" Name="FetchUnit_routed_bb.dcp"/>
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<File Type="BITSTR-LTX" Name="FetchUnit.ltx"/>
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<File Type="BITSTR-MMI" Name="FetchUnit.mmi"/>
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<File Type="BITSTR-SYSDEF" Name="FetchUnit.sysdef"/>
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<File Type="ROUTE-TIMING-PB" Name="FetchUnit_timing_summary_routed.pb"/>
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<File Type="POSTROUTE-PHYSOPT-DCP" Name="FetchUnit_postroute_physopt.dcp"/>
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<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="FetchUnit_postroute_physopt_bb.dcp"/>
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<File Type="BG-BIT" Name="FetchUnit.bit"/>
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<File Type="BITSTR-RBT" Name="FetchUnit.rbt"/>
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<File Type="BITSTR-NKY" Name="FetchUnit.nky"/>
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<File Type="BG-DRC" Name="FetchUnit.drc"/>
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<File Type="RDI-RDI" Name="FetchUnit.vdi"/>
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<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
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<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/ALU.v">
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<FileInfo>
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|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
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|
<Attr Name="UsedIn" Val="simulation"/>
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|
</FileInfo>
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|
</File>
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|
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
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|
</FileInfo>
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|
</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="FetchUnit"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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<Filter Type="Constrs"/>
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<Config>
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
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<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
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<Filter Type="Utils"/>
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<Config>
|
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
</Config>
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|
</FileSet>
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
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|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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|
</Strategy>
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|
</GenRun>
|