69 lines
3.1 KiB
Plaintext
69 lines
3.1 KiB
Plaintext
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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| Date : Sat Apr 6 17:34:31 2019
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| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
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| Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
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| Design : CPU9bits
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| Device : xc7k160ti
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Control Set Information
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Table of Contents
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-----------------
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1. Summary
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2. Histogram
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3. Flip-Flop Distribution
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4. Detailed Control Set Information
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1. Summary
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----------
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+----------------------------------------------------------+-------+
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| Status | Count |
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+----------------------------------------------------------+-------+
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| Number of unique control sets | 3 |
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| Unused register locations in slices containing registers | 14 |
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+----------------------------------------------------------+-------+
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2. Histogram
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------------
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+--------+--------------+
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| Fanout | Control Sets |
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+--------+--------------+
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| 9 | 2 |
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| 16+ | 1 |
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+--------+--------------+
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3. Flip-Flop Distribution
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-------------------------
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+--------------+-----------------------+------------------------+-----------------+--------------+
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| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
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+--------------+-----------------------+------------------------+-----------------+--------------+
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| No | No | No | 0 | 0 |
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| No | No | Yes | 0 | 0 |
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| No | Yes | No | 40 | 11 |
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| Yes | No | No | 0 | 0 |
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| Yes | No | Yes | 0 | 0 |
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| Yes | Yes | No | 18 | 6 |
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+--------------+-----------------------+------------------------+-----------------+--------------+
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4. Detailed Control Set Information
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-----------------------------------
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+----------------+------------------------+------------------+------------------+----------------+
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| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
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+----------------+------------------------+------------------+------------------+----------------+
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| clk_IBUF_BUFG | pipe2/E[0] | reset_IBUF | 3 | 9 |
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| clk_IBUF_BUFG | pipe2/Dout_reg[5]_0[0] | reset_IBUF | 3 | 9 |
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| clk_IBUF_BUFG | | reset_IBUF | 11 | 40 |
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+----------------+------------------------+------------------+------------------+----------------+
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