158 lines
7.7 KiB
Plaintext
158 lines
7.7 KiB
Plaintext
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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| Date : Sat Apr 6 17:35:04 2019
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| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
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| Command : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
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| Design : CPU9bits
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| Device : xc7k160tifbg484-2L
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| Design State : routed
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| Grade : industrial
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| Process : typical
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| Characterization : Production
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Power Report
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Table of Contents
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-----------------
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1. Summary
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1.1 On-Chip Components
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1.2 Power Supply Summary
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1.3 Confidence Level
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2. Settings
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2.1 Environment
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2.2 Clock Constraints
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3. Detailed Reports
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3.1 By Hierarchy
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1. Summary
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----------
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+--------------------------+--------------+
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| Total On-Chip Power (W) | 10.632 |
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| Design Power Budget (W) | Unspecified* |
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| Power Budget Margin (W) | NA |
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| Dynamic (W) | 10.494 |
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| Device Static (W) | 0.137 |
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| Effective TJA (C/W) | 2.5 |
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| Max Ambient (C) | 73.7 |
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| Junction Temperature (C) | 51.3 |
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| Confidence Level | Low |
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| Setting File | --- |
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| Simulation Activity File | --- |
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| Design Nets Matched | NA |
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+--------------------------+--------------+
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* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
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1.1 On-Chip Components
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----------------------
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+----------------+-----------+----------+-----------+-----------------+
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| On-Chip | Power (W) | Used | Available | Utilization (%) |
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+----------------+-----------+----------+-----------+-----------------+
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| Slice Logic | 0.768 | 132 | --- | --- |
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| LUT as Logic | 0.719 | 54 | 101400 | 0.05 |
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| Register | 0.043 | 58 | 202800 | 0.03 |
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| BUFG | 0.005 | 1 | 32 | 3.13 |
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| Others | 0.000 | 5 | --- | --- |
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| Signals | 0.881 | 109 | --- | --- |
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| Block RAM | 0.060 | 0.5 | 325 | 0.15 |
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| I/O | 8.785 | 12 | 285 | 4.21 |
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| Static Power | 0.137 | | | |
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| Total | 10.632 | | | |
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+----------------+-----------+----------+-----------+-----------------+
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1.2 Power Supply Summary
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------------------------
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+-----------+-------------+-----------+-------------+------------+
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| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
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+-----------+-------------+-----------+-------------+------------+
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| Vccint | 0.950 | 1.868 | 1.799 | 0.070 |
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| Vccaux | 1.800 | 0.738 | 0.719 | 0.020 |
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| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
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| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
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| Vcco18 | 1.800 | 4.161 | 4.160 | 0.001 |
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| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
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| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
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| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
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| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
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| Vccbram | 0.950 | 0.006 | 0.005 | 0.002 |
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| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
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| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
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| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 |
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| Vccadc | 1.800 | 0.018 | 0.000 | 0.018 |
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+-----------+-------------+-----------+-------------+------------+
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1.3 Confidence Level
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--------------------
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+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
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| User Input Data | Confidence | Details | Action |
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+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
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| Design implementation state | High | Design is routed | |
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| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
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| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
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| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
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| Device models | High | Device models are Production | |
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| Overall confidence level | Low | | |
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+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
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2. Settings
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-----------
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2.1 Environment
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---------------
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+-----------------------+--------------------------+
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| Ambient Temp (C) | 25.0 |
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| ThetaJA (C/W) | 2.5 |
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| Airflow (LFM) | 250 |
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| Heat Sink | medium (Medium Profile) |
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| ThetaSA (C/W) | 4.2 |
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| Board Selection | medium (10"x10") |
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| # of Board Layers | 12to15 (12 to 15 Layers) |
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| Board Temperature (C) | 25.0 |
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+-----------------------+--------------------------+
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2.2 Clock Constraints
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---------------------
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+-------+--------+-----------------+
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| Clock | Domain | Constraint (ns) |
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+-------+--------+-----------------+
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3. Detailed Reports
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-------------------
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3.1 By Hierarchy
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----------------
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+------------+-----------+
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| Name | Power (W) |
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+------------+-----------+
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| CPU9bits | 10.494 |
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| EM | 0.099 |
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| dM | 0.099 |
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| FD | 0.424 |
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| FetchU | 0.179 |
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| PC | 0.179 |
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| RF | 0.244 |
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| r0 | 0.133 |
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| r1 | 0.112 |
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| W | 0.301 |
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| mux5 | 0.301 |
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| pipe1 | 0.782 |
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| pipe2 | 0.087 |
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+------------+-----------+
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