67 lines
3.1 KiB
Tcl
67 lines
3.1 KiB
Tcl
#
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# Synthesis run script generated by Vivado
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#
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set TIME_start [clock seconds]
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proc create_report { reportName command } {
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set status "."
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append status $reportName ".fail"
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if { [file exists $status] } {
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eval file delete [glob $status]
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}
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send_msg_id runtcl-4 info "Executing : $command"
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set retval [eval catch { $command } msg]
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if { $retval != 0 } {
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set fp [open $status w]
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close $fp
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send_msg_id runtcl-5 warning "$msg"
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}
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}
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set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-10176-DESKTOP-8QFGS52/incrSyn
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set_msg_config -id {Synth 8-256} -limit 10000
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set_msg_config -id {Synth 8-638} -limit 10000
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create_project -in_memory -part xc7k160tifbg484-2L
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set_param project.singleFileAddWarning.threshold 0
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set_param project.compositeFile.enableAutoGeneration 0
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set_param synth.vivado.isSynthRun true
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set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project]
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set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project]
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set_property default_lib xil_defaultlib [current_project]
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set_property target_language Verilog [current_project]
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set_property ip_output_repo c:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project]
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set_property ip_cache_permissions {read write} [current_project]
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read_verilog -library xil_defaultlib {
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v
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}
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# Mark all dcp files as not used in implementation to prevent them from being
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# stitched into the results of this synthesis run. Any black boxes in the
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# design are intentionally left as such for best results. Dcp files will be
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# stitched into the design at a later time, either when this synthesis run is
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# opened, or when it is stitched into a dependent implementation run.
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foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
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set_property used_in_implementation false $dcp
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}
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set_param ips.enableIPCacheLiteLoad 1
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close [open __synthesis_is_running__ w]
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synth_design -top CPU9bits -part xc7k160tifbg484-2L
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# disable binary constraint mode for synth run checkpoints
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set_param constraints.enableBinaryConstraints false
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write_checkpoint -force -noxdef CPU9bits.dcp
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create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb"
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file delete __synthesis_is_running__
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close [open __synthesis_is_complete__ w]
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