Files
WMU-ECE-3570-Lab/lab2CA.sim/sim_1/behav/xsim/add1bit_tb_vlog.prj

10 lines
227 B
Plaintext

# compile verilog/system verilog design source files
verilog xil_defaultlib \
"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort