cb91f6656a
I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
10 lines
227 B
Plaintext
10 lines
227 B
Plaintext
# compile verilog/system verilog design source files
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verilog xil_defaultlib \
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"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
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# compile glbl module
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verilog xil_defaultlib "glbl.v"
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# Do not sort compile order
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nosort
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