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WMU-ECE-3570-Lab/lab2CA.sim/sim_1/behav/xsim/fetchUnit_tb_vlog.prj
2019-02-20 11:31:25 -05:00

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# compile verilog/system verilog design source files
verilog xil_defaultlib \
"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
"../../../../lab2CA.srcs/sources_1/new/FetchUnit.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort