93 lines
1.5 KiB
Verilog
93 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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module CPU9bits(
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input wire reset, clk,
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output wire [8:0] result,
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output wire done
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);
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wire [8:0] RFIn,FUAddr;
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wire [1:0] instr;
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wire fetchBranch, RegEn;
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wire [50:0] FDOut, FDPipOut;
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wire [61:0] EMOut, EMPipOut;
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assign result = RFIn;
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FDModule FD(
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.reset(reset),
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.clk(clk),
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.FUIdx(fetchBranch),
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.En(RegEn),
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.RFIn(RFIn),
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.AddrIn(FUAddr),
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.RFIdx(instr),
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.result(FDOut),
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.done(done)
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);
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fDPipReg pipe1(
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.clk(clk),
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.reset(reset),
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.En(RegEn),
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.Din(FDOut),
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.Dout(FDPipOut)
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);
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EMModule EM(
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.reset(reset),
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.clk(clk),
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.PipIn(FDPipOut),
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.PipOut(EMOut)
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);
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eMPipReg pipe2(
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.clk(clk),
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.reset(reset),
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.En(RegEn),
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.Din(EMOut),
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.Dout(EMPipOut)
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);
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WMUdule W(
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.PipIn(EMPipOut),
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.RFIn(RFIn),
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.FUAddr(FUAddr),
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.instr(instr),
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.fetchBranch(fetchBranch),
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.RegEn(RegEn)
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);
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endmodule
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module CPU9bits_tb();
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reg clk, reset;
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wire done;
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wire [8:0] result;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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CPU9bits CPU9bits0(
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.reset(reset),
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.clk(clk),
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.done(done),
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.result(result));
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initial begin
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#5
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reset = 1'b1;
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#10
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reset = 1'b0;
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#50
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$finish;
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end
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endmodule
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