121 lines
2.6 KiB
Verilog
121 lines
2.6 KiB
Verilog
`timescale 1ns / 1ps
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module EMModule(
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input wire reset, clk,
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input wire [50:0] PipIn,
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output wire [61:0] PipOut
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);
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wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn,dataMemOut,SE1N,SE2N,SE3N,bankOP,jumpNeg;
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wire [3:0] aluOp;
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wire [2:0] FU;
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wire [1:0] bankS;
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wire addiS, RegEn, loadS, fetchBranch, cout0, cout1, link, js, dataMemEn;
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assign instr = PipIn[50:42];
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assign op0 = PipIn[41:33];
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assign op1 = PipIn[32:24];
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assign PCout = PipIn[23:15];
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assign addiS = PipIn[14];
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assign RegEn = PipIn[13];
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assign loadS = PipIn[12];
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assign link = PipIn[11];
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assign js = PipIn[10];
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assign dataMemEn = PipIn[9];
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assign aluOp = PipIn[8:5];
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assign FU = PipIn[4:2];
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assign bankS = PipIn[1:0];
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assign PipOut = {RegEn,PCout,bankOP,FUAddr,AluOut,dataMemOut,AddiOut,instr[4:3],bankS[0],loadS,link,addiS,fetchBranch}; // concat all signals into one
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dataMemory dM(
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.clk(clk),
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.writeEnable(dataMemEn),
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.writeData(op0),
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.address(op1),
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.readData(dataMemOut)
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);
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RegFile Bank(
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.clk(clk),
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.reset(reset),
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.write_index(instr[2:1]),
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.op0_idx(instr[2:1]),
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.op1_idx(2'b00),//Doesn't matter
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.write_data(op0),
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.op0(bankOP),
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.op1(),
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.En(bankS[1])
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);
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ALU alu(
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.opcode(aluOp),
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.operand0(op0),
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.operand1(op1),
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.result(AluOut)
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);
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add_9bit JBAdder(
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.A(PCout),
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.B(JBRes),
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.Cin(1'b0),
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.Sum(FUJB),
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.Cout(cout0)
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);
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mux_2_1 mux0(
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.A(op0),
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.B(FUJB),
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.out(FUAddr),
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.switch(FU[1])
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);
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twos_compliment_9bit two_comp0(
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.A({4'b0000,instr[4:0]}),
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.B(jumpNeg)
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);
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mux_2_1 mux1(
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.A({4'b0000,instr[4:0]}),
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.B(jumpNeg),
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.out(SE2N),
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.switch(js)
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);
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mux_2_1 mux2(
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.A(SE2N), //Jump -- Change with signer module!
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.B(SE1N),//Branch -- Change with signer module!
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.out(JBRes),
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.switch(FU[2])
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);
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sign_extend_3bit SE1(
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.A(instr[2:0]),
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.B(SE1N)
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);
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bit1_mux_2_1 BranMux( // BEQ MUX
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.A(FU[0]),
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.B(AluOut[0]),
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.out(fetchBranch),
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.switch(FU[2]) // FU[2] only goes high when BEQ
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);
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///--------------------------Addi Stuff
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add_9bit Addier(
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.A(SE3N), // Change with signer module!
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.B(op0),
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.Cin(1'b0),
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.Sum(AddiOut),
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.Cout(cout1)
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);
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sign_extend_3bit SE3(
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.A(instr[2:0]),
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.B(SE3N)
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);
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endmodule
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