WilliamMiceli fd22d5c7e6 Added 16:1 MUX for our ALU

2019-02-15 15:33:02 -05:00

..

BasicModules.v

Added 16:1 MUX for our ALU

2019-02-15 15:33:02 -05:00

fetchFile.v

fetch unit

2019-02-15 11:20:14 -05:00

FetchUnit.v

Modularized project; mux, clock, and reg done; Progress on RegFile

2019-02-15 12:24:26 -05:00

lab2testing.v

Modularized project; mux, clock, and reg done; Progress on RegFile

2019-02-15 12:24:26 -05:00

RegFile.v

Removed comment blocks

2019-02-15 14:34:59 -05:00