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Adding documentation for power design

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Stephen
2021-04-09 10:43:29 -04:00
parent 2146daacfb
commit 7acd7729d6
1440 changed files with 1708 additions and 1661 deletions
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2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2crc_2crc__ex1__build_signature_8c.tex
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@@ -17,7 +17,7 @@ void \mbox{\hyperlink{_m_s_p430_f5xx__6xx_2crc_2crc__ex1__build_signature_8c_a62
CRC -\/ Build Signature and Rebuild to test.
The CRC is first used to build a signature using a seed and multiple data values. This signature is considered as the checksum and can be sent by a UART connection along with the data to verify the correct data has been sent. The second half of this program is used to test the CRC checksum of the data that has been created, by recreating the same checksum and comparing it to the first checksum. If the two checksum are equal, then P1.\+0 is set and the LED is turned on. Breakpoints can be set before the CRC\+\_\+set\+Data() function to observe the CRC register values and see the subsequent signatures before/after each data set.\hypertarget{_m_s_p430_f5xx__6xx_2crc_2crc__ex1__build_signature_8c_autotoc_md37}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2crc_2crc__ex1__build_signature_8c_autotoc_md37}
The CRC is first used to build a signature using a seed and multiple data values. This signature is considered as the checksum and can be sent by a UART connection along with the data to verify the correct data has been sent. The second half of this program is used to test the CRC checksum of the data that has been created, by recreating the same checksum and comparing it to the first checksum. If the two checksum are equal, then P1.\+0 is set and the LED is turned on. Breakpoints can be set before the CRC\+\_\+set\+Data() function to observe the CRC register values and see the subsequent signatures before/after each data set.\hypertarget{_m_s_p430_f5xx__6xx_2crc_2crc__ex1__build_signature_8c_autotoc_md41}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2crc_2crc__ex1__build_signature_8c_autotoc_md41}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2dma_2dma__ex1__repeated_block_8c.tex
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@@ -17,7 +17,7 @@ void \mbox{\hyperlink{_m_s_p430_f5xx__6xx_2dma_2dma__ex1__repeated_block_8c_a628
DMA -\/ Repeated Block Transfer to-\/and-\/from RAM, Software Trigger.
A 16 word block from 1C00-\/1\+C1\+Fh is transfered to 1C20h-\/1\+C3fh using DMA0 in a burst block using software DMAREQ trigger. After each transfer, source, destination and DMA size are reset to initial software setting because DMA transfer mode 5 is used. P1.\+0 is toggled during DMA transfer only for demonstration purposes. $\ast$$\ast$ RAM location 0x1\+C00 -\/ 0x1\+C3F used -\/ make sure no compiler conflict $\ast$$\ast$ ACLK = REFO = 32k\+Hz, MCLK = SMCLK = default DCO 1048576Hz\hypertarget{_m_s_p430_f5xx__6xx_2dma_2dma__ex1__repeated_block_8c_autotoc_md38}{}\doxysubsubsection{Tested on MSP430\+F5529, MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2dma_2dma__ex1__repeated_block_8c_autotoc_md38}
A 16 word block from 1C00-\/1\+C1\+Fh is transfered to 1C20h-\/1\+C3fh using DMA0 in a burst block using software DMAREQ trigger. After each transfer, source, destination and DMA size are reset to initial software setting because DMA transfer mode 5 is used. P1.\+0 is toggled during DMA transfer only for demonstration purposes. $\ast$$\ast$ RAM location 0x1\+C00 -\/ 0x1\+C3F used -\/ make sure no compiler conflict $\ast$$\ast$ ACLK = REFO = 32k\+Hz, MCLK = SMCLK = default DCO 1048576Hz\hypertarget{_m_s_p430_f5xx__6xx_2dma_2dma__ex1__repeated_block_8c_autotoc_md42}{}\doxysubsubsection{Tested on MSP430\+F5529, MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2dma_2dma__ex1__repeated_block_8c_autotoc_md42}
/$\vert$$|$ XIN$\vert$-\/ $\vert$ $\vert$ $\vert$ 32k\+Hz --$\vert$\+RST XOUT$\vert$-\/ $\vert$ $\vert$ $\vert$ P1.\+0$\vert$-\/$>$ LED $\vert$ $\vert$
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c.tex
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@@ -71,7 +71,7 @@ Referenced by USCI\+\_\+\+A0\+\_\+\+ISR().
SPI slave talks to SPI master using 3-\/wire mode. Data is received from master and data from slave is then transmitted back to master. USCI RX ISR is used to handle communication, CPU normally in LPM4. Prior to initial data exchange, master pulses slaves RST for complete reset.
Use with eusci\+\_\+spi\+\_\+ex1\+\_\+master code example. If the slave is in debug mode, the reset signal from the master will conflict with slave\textquotesingle{}s JTAG; to work around, use IAR\textquotesingle{}s \char`\"{}\+Release JTAG on Go\char`\"{} on slave device. If breakpoints are set in slave RX ISR, master must stopped also to avoid overrunning slave RXBUF.\hypertarget{_m_s_p430_f5xx__6xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c_autotoc_md39}{}\doxysubsubsection{Tesed on MSP430\+F67791A}\label{_m_s_p430_f5xx__6xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c_autotoc_md39}
Use with eusci\+\_\+spi\+\_\+ex1\+\_\+master code example. If the slave is in debug mode, the reset signal from the master will conflict with slave\textquotesingle{}s JTAG; to work around, use IAR\textquotesingle{}s \char`\"{}\+Release JTAG on Go\char`\"{} on slave device. If breakpoints are set in slave RX ISR, master must stopped also to avoid overrunning slave RXBUF.\hypertarget{_m_s_p430_f5xx__6xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c_autotoc_md43}{}\doxysubsubsection{Tesed on MSP430\+F67791A}\label{_m_s_p430_f5xx__6xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c_autotoc_md43}
/$\vert$\textbackslash{} $\vert$ $\vert$ $\vert$ $\vert$ $\vert$ Master---+-\/$>$$\vert$\+RST $\vert$ $\vert$ $\vert$ $\vert$ P3.\+1$\vert$-\/$>$ Data Out (UCA0\+SIMO) $\vert$ $\vert$ $\vert$ P3.\+0$\vert$$<$-\/ Data In (UCA0\+SOMI) $\vert$ $\vert$ $\vert$ P3.\+2$\vert$$<$-\/ Serial Clock Out (UCA0\+CLK)
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2eusci__b__spi_2eusci__b__spi__ex1__slave_8c.tex
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@@ -71,7 +71,7 @@ Referenced by USCI\+\_\+\+B0\+\_\+\+ISR().
SPI slave talks to SPI master using 3-\/wire mode. Data is received from master and data from slave is then transmitted back to master. USCI RX ISR is used to handle communication, CPU normally in LPM4. Prior to initial data exchange, master pulses slaves RST for complete reset.
Use with eusci\+\_\+spi\+\_\+ex1\+\_\+master code example. If the slave is in debug mode, the reset signal from the master will conflict with slave\textquotesingle{}s JTAG; to work around, use IAR\textquotesingle{}s \char`\"{}\+Release JTAG on Go\char`\"{} on slave device. If breakpoints are set in slave RX ISR, master must stopped also to avoid overrunning slave RXBUF.\hypertarget{_m_s_p430_f5xx__6xx_2eusci__b__spi_2eusci__b__spi__ex1__slave_8c_autotoc_md40}{}\doxysubsubsection{Tesed on MSP430\+F67791A}\label{_m_s_p430_f5xx__6xx_2eusci__b__spi_2eusci__b__spi__ex1__slave_8c_autotoc_md40}
Use with eusci\+\_\+spi\+\_\+ex1\+\_\+master code example. If the slave is in debug mode, the reset signal from the master will conflict with slave\textquotesingle{}s JTAG; to work around, use IAR\textquotesingle{}s \char`\"{}\+Release JTAG on Go\char`\"{} on slave device. If breakpoints are set in slave RX ISR, master must stopped also to avoid overrunning slave RXBUF.\hypertarget{_m_s_p430_f5xx__6xx_2eusci__b__spi_2eusci__b__spi__ex1__slave_8c_autotoc_md44}{}\doxysubsubsection{Tesed on MSP430\+F67791A}\label{_m_s_p430_f5xx__6xx_2eusci__b__spi_2eusci__b__spi__ex1__slave_8c_autotoc_md44}
/$\vert$\textbackslash{} $\vert$ $\vert$ $\vert$ $\vert$ $\vert$ Master---+-\/$>$$\vert$\+RST $\vert$ $\vert$ $\vert$ $\vert$ P2.\+6$\vert$-\/$>$ Data Out (UCB0\+SIMO) $\vert$ $\vert$ $\vert$ P2.\+5$\vert$$<$-\/ Data In (UCB0\+SOMI) $\vert$ $\vert$ $\vert$ P2.\+7$\vert$-\/$>$ Serial Clock Out (UCB0\+CLK)
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 32x32 Signed Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RES0, RES1, RES2 and RES3.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md45}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md45}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md49}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md49}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

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Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 32x32 Signed Multiply Accumalate
Hardware multiplier is used to multiply-\/accumalate a set of numbers. The first calculation is automatically initiated after the second operand is loaded. A second multiply-\/accumulate operation is performed next. Results are stored in RES0, RES1, RES2 and RES3. SUMEXT contains the extended sign of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md46}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md46}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md50}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md50}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 32x32 Unsigned Multiply Accumalate
Hardware multiplier is used to multiply-\/accumalate a set of numbers. The first calculation is automatically initiated after the second operand is loaded. A second multiply-\/accumulate operation is performed next. Results are stored in RES0, RES1, RES2 and RES3. SUMEXT contains the extended sign of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md47}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md47}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md51}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md51}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

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Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex13__saturation_underflow_8c.tex
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@@ -45,7 +45,7 @@ MPY -\/ Saturation Mpode Underflow Test
Description\+: The example illustrates a special case showing underflow. Underflow occurs when adding 2 negative numbers yields a positive result. By having the saturation mode enabled, the result if rounded off to the highest negative number (0x8000.\+0000 for 16 bit). Results can be viewed in the debugger window.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex13__saturation_underflow_8c_autotoc_md48}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex13__saturation_underflow_8c_autotoc_md48}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex13__saturation_underflow_8c_autotoc_md52}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex13__saturation_underflow_8c_autotoc_md52}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

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Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex14__saturation_overflow_8c.tex
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@@ -45,7 +45,7 @@ MPY -\/ Saturation Mode Overflow Test
The example illustrates a special case showing overflow. The addition result of 2 positive numbers may exceed the highest positive number (0x7\+FFF FFFF for 32 bit result) due to overflow indicating a negative result. By having the saturation mode enabled, this result can be truncated off to this highest positive number. Results with and without saturation mode are shown.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex14__saturation_overflow_8c_autotoc_md49}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex14__saturation_overflow_8c_autotoc_md49}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex14__saturation_overflow_8c_autotoc_md53}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex14__saturation_overflow_8c_autotoc_md53}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex15__fraction_mode_8c.tex
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@@ -43,7 +43,7 @@ MPY -\/ Fractional mode, Q15 multiplication
The example illustrates multiplication of 2 Q15 numbers in fractional mode. The result is a Q15 (15 bit) number stored in the RES1 register. It can be viewed in the debugger window.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex15__fraction_mode_8c_autotoc_md50}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex15__fraction_mode_8c_autotoc_md50}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex15__fraction_mode_8c_autotoc_md54}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex15__fraction_mode_8c_autotoc_md54}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 16x16 Unsigned Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RESLO and RESHI.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c_autotoc_md51}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c_autotoc_md51}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c_autotoc_md55}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c_autotoc_md55}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 8x8 Unsigned Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RESLO and RESHI.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c_autotoc_md52}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c_autotoc_md52}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c_autotoc_md56}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c_autotoc_md56}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c.tex
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@@ -45,7 +45,7 @@ MPY -\/ 16x16 Signed Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RESLO, RESHI and SUMEXT = FFFF if result is negative, SUMEXT = 0 otherwise. Result is also stored as Result variable.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c_autotoc_md53}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c_autotoc_md53}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c_autotoc_md57}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c_autotoc_md57}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

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Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 8x8 Signed Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RESLO, RESHI and SUMEXT = FFFF if result is negative, SUMEXT = 0 otherwise.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c_autotoc_md54}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c_autotoc_md54}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c_autotoc_md58}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c_autotoc_md58}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 16x16 Unsigned Multiply Accumulate
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the carry of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c_autotoc_md55}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c_autotoc_md55}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c_autotoc_md59}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c_autotoc_md59}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c.tex
View File

@@ -17,7 +17,7 @@ void \mbox{\hyperlink{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex6__8bit_unsigned_mult
MPY -\/ 8x8 Unsigned Multiply Accumulate
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the carry of the result.\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c_autotoc_md56}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c_autotoc_md56}
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the carry of the result.\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c_autotoc_md60}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c_autotoc_md60}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 16x16 Signed Multiply Accumulate
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply-\/accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the extended sign of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c_autotoc_md57}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c_autotoc_md57}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c_autotoc_md61}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c_autotoc_md61}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 8x8 Signed Multiply Accumulate
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the extended sign of result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c_autotoc_md58}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c_autotoc_md58}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c_autotoc_md62}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c_autotoc_md62}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c.tex
View File

@@ -41,7 +41,7 @@ MPY -\/ 32x32 Unsigned Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RES0, RES1, RES2 and RES3.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c_autotoc_md59}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c_autotoc_md59}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c_autotoc_md63}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f5xx__6xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c_autotoc_md63}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2rtc__c_2rtc__c__ex1__calendarmode_8c.tex
View File

@@ -57,7 +57,7 @@ RTC\+\_\+C in Calendar mode, Interruptions every 1s, 1m, and 5th day of week at
This program demonstrates the RTC mode by triggering an interrupt every second and minute. This code toggles P1.\+0 every second. This code recommends an external LFXT1 crystal for RTC accuracy. Note that if XT1 is not present the code loops in an infinite loop. ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
NOTE\+: Refer device header file and pass in baseaddress parameter for RTC\+\_\+C as RTC\+\_\+\+C\+\_\+\+BASE or RTC\+\_\+\+CE\+\_\+\+BASE as defined in User\textquotesingle{}s guide\hypertarget{_m_s_p430_f5xx__6xx_2rtc__c_2rtc__c__ex1__calendarmode_8c_autotoc_md64}{}\doxysubsubsection{Tested On\+: MSP430\+F6736}\label{_m_s_p430_f5xx__6xx_2rtc__c_2rtc__c__ex1__calendarmode_8c_autotoc_md64}
NOTE\+: Refer device header file and pass in baseaddress parameter for RTC\+\_\+C as RTC\+\_\+\+C\+\_\+\+BASE or RTC\+\_\+\+CE\+\_\+\+BASE as defined in User\textquotesingle{}s guide\hypertarget{_m_s_p430_f5xx__6xx_2rtc__c_2rtc__c__ex1__calendarmode_8c_autotoc_md68}{}\doxysubsubsection{Tested On\+: MSP430\+F6736}\label{_m_s_p430_f5xx__6xx_2rtc__c_2rtc__c__ex1__calendarmode_8c_autotoc_md68}
/$\vert$\textbackslash{} $\vert$ XIN$\vert$-\/ $\vert$ $\vert$ $\vert$ 32k\+Hz ---$\vert$\+RST XOUT$\vert$-\/ $\vert$ $\vert$ $\vert$ P1.\+0 $\vert$-\/-\/$>$ Toggles every second $\vert$ $\vert$
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex1__pwm_single_8c.tex
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@@ -34,7 +34,7 @@ Definition at line 64 of file timer\+\_\+a\+\_\+ex1\+\_\+pwm\+Single.\+c.
Timer\+\_\+\+A3, PWM TA1.\+1, Up Mode, DCO SMCLK
Description\+: This program generates PWM outputs on P2.\+2 using Timer1\+\_\+A configured for up mode. The value , TIMER\+\_\+\+PERIOD, defines the PWM period and the value DUTY\+\_\+\+CYCLE the PWM duty cycle. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$500us with a 75\% duty cycle on P2.\+2 ACLK = n/a, SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex1__pwm_single_8c_autotoc_md65}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex1__pwm_single_8c_autotoc_md65}
Description\+: This program generates PWM outputs on P2.\+2 using Timer1\+\_\+A configured for up mode. The value , TIMER\+\_\+\+PERIOD, defines the PWM period and the value DUTY\+\_\+\+CYCLE the PWM duty cycle. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$500us with a 75\% duty cycle on P2.\+2 ACLK = n/a, SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex1__pwm_single_8c_autotoc_md69}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex1__pwm_single_8c_autotoc_md69}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex2__continous_mode_operation_with_c_c_r0_interrupt_8c.tex
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@@ -24,7 +24,7 @@ void \mbox{\hyperlink{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex2__continous_mo
TIMER\+\_\+A, Toggle P1.\+0, CCR0 Cont. Mode ISR, DCO SMCLK
Toggle P1.\+0 using software and TA\+\_\+0 ISR. Toggles every 50000 SMCLK cycles. SMCLK provides clock source for TACLK. During the TA\+\_\+0 ISR, P1.\+0 is toggled and 50000 clock cycles are added to CCR0. TA\+\_\+0 ISR is triggered every 50000 cycles. CPU is normally off and used only during TA\+\_\+\+ISR. ACLK = n/a, MCLK = SMCLK = TACLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex2__continous_mode_operation_with_c_c_r0_interrupt_8c_autotoc_md66}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex2__continous_mode_operation_with_c_c_r0_interrupt_8c_autotoc_md66}
Toggle P1.\+0 using software and TA\+\_\+0 ISR. Toggles every 50000 SMCLK cycles. SMCLK provides clock source for TACLK. During the TA\+\_\+0 ISR, P1.\+0 is toggled and 50000 clock cycles are added to CCR0. TA\+\_\+0 ISR is triggered every 50000 cycles. CPU is normally off and used only during TA\+\_\+\+ISR. ACLK = n/a, MCLK = SMCLK = TACLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex2__continous_mode_operation_with_c_c_r0_interrupt_8c_autotoc_md70}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex2__continous_mode_operation_with_c_c_r0_interrupt_8c_autotoc_md70}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c.tex
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@@ -19,7 +19,7 @@ void \mbox{\hyperlink{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex3__continous_mo
TIMER\+\_\+A, Toggle P1.\+0, Overflow ISR, 32k\+Hz ACLK
Description\+: Toggle P1.\+0 using software and the TIMER\+\_\+A overflow ISR. In this example an ISR triggers when TB overflows. Inside the ISR P1.\+0 is toggled. Toggle rate is exactly 0.\+25\+Hz = \mbox{[}32k\+Hz/\+FFFFh\mbox{]}/2. Proper use of the TAIV interrupt vector generator is demonstrated. ACLK = TBCLK = 32k\+Hz, MCLK = SMCLK = default DCO $\sim$ 1.\+045\+MHz\hypertarget{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c_autotoc_md67}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c_autotoc_md67}
Description\+: Toggle P1.\+0 using software and the TIMER\+\_\+A overflow ISR. In this example an ISR triggers when TB overflows. Inside the ISR P1.\+0 is toggled. Toggle rate is exactly 0.\+25\+Hz = \mbox{[}32k\+Hz/\+FFFFh\mbox{]}/2. Proper use of the TAIV interrupt vector generator is demonstrated. ACLK = TBCLK = 32k\+Hz, MCLK = SMCLK = default DCO $\sim$ 1.\+045\+MHz\hypertarget{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c_autotoc_md71}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c_autotoc_md71}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c.tex
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@@ -46,7 +46,7 @@ Definition at line 68 of file timer\+\_\+a\+\_\+ex4\+\_\+pwm\+Multiple\+Up\+Down
Timer\+\_\+\+A3, PWM TA1.\+1-\/2, Up/\+Down Mode, DCO SMCLK
Description\+: This program generates two PWM outputs on P2.\+0,P2.\+1 using Timer1\+\_\+A configured for up/down mode. The value in CCR0, 128, defines the PWM period/2 and the values in CCR1 and CCR2 the PWM duty cycles. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$233us with a 75\% duty cycle on P2.\+0 and 25\% on P2.\+1. SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c_autotoc_md68}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c_autotoc_md68}
Description\+: This program generates two PWM outputs on P2.\+0,P2.\+1 using Timer1\+\_\+A configured for up/down mode. The value in CCR0, 128, defines the PWM period/2 and the values in CCR1 and CCR2 the PWM duty cycles. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$233us with a 75\% duty cycle on P2.\+0 and 25\% on P2.\+1. SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c_autotoc_md72}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c_autotoc_md72}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c.tex
View File

@@ -44,7 +44,7 @@ Definition at line 65 of file timer\+\_\+a\+\_\+ex5\+\_\+pwm\+Multiple\+Up.\+c.
\doxysubsubsection{\texorpdfstring{TIMER\_PERIOD}{TIMER\_PERIOD}}
{\footnotesize\ttfamily \#define TIMER\+\_\+\+PERIOD~511}
This program generates two PWM outputs on P2.\+0,P2.\+1 using Timer1\+\_\+A configured for up mode. The value in CCR0, 512-\/1, defines the PWM period and the values in CCR1 and CCR2 the PWM duty cycles. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$500us with a 75\% duty cycle on P2.\+2 and 25\% on P2.\+3. ACLK = n/a, SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c_autotoc_md69}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c_autotoc_md69}
This program generates two PWM outputs on P2.\+0,P2.\+1 using Timer1\+\_\+A configured for up mode. The value in CCR0, 512-\/1, defines the PWM period and the values in CCR1 and CCR2 the PWM duty cycles. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$500us with a 75\% duty cycle on P2.\+2 and 25\% on P2.\+3. ACLK = n/a, SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c_autotoc_md73}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c_autotoc_md73}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c.tex
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@@ -32,7 +32,7 @@ Definition at line 65 of file timer\+\_\+a\+\_\+ex6\+\_\+up\+Down\+Mode\+Operati
\doxysubsubsection{\texorpdfstring{TIMER\_A\_PERIOD}{TIMER\_A\_PERIOD}}
{\footnotesize\ttfamily \#define TIMER\+\_\+\+A\+\_\+\+PERIOD~250}
Toggle P1.\+7 using hardware TA1.\+0 output. Timer1\+\_\+A is configured for up/down mode with CCR0 defining period, TA1.\+0 also output on P1.\+7. In this example, CCR0 is loaded with 250 and TA1.\+0 will toggle P1.\+7 at TACLK/2$\ast$250. Thus the output frequency on P1.\+7 will be the TACLK/1000. No CPU or software resources required. As coded with TACLK = SMCLK, P1.\+7 output frequency is $\sim$1.045M/1000. SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c_autotoc_md70}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c_autotoc_md70}
Toggle P1.\+7 using hardware TA1.\+0 output. Timer1\+\_\+A is configured for up/down mode with CCR0 defining period, TA1.\+0 also output on P1.\+7. In this example, CCR0 is loaded with 250 and TA1.\+0 will toggle P1.\+7 at TACLK/2$\ast$250. Thus the output frequency on P1.\+7 will be the TACLK/1000. No CPU or software resources required. As coded with TACLK = SMCLK, P1.\+7 output frequency is $\sim$1.045M/1000. SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c_autotoc_md74}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c_autotoc_md74}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex1__continuous_mode_c_c_r0_8c.tex
View File

@@ -24,7 +24,7 @@ void \mbox{\hyperlink{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex1__continuous_m
Timer\+\_\+B, Toggle P1.\+0, CCR0 Cont. Mode ISR, DCO SMCLK
Description\+: Toggle P1.\+0 using software and TB\+\_\+0 ISR. Toggles every 50000 SMCLK cycles. SMCLK provides clock source for TBCLK. During the TB\+\_\+0 ISR, P1.\+0 is toggled and 50000 clock cycles are added to CCR0. TB\+\_\+0 ISR is triggered every 50000 cycles. CPU is normally off and used only during TB\+\_\+\+ISR. ACLK = n/a, MCLK = SMCLK = TBCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex1__continuous_mode_c_c_r0_8c_autotoc_md71}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex1__continuous_mode_c_c_r0_8c_autotoc_md71}
Description\+: Toggle P1.\+0 using software and TB\+\_\+0 ISR. Toggles every 50000 SMCLK cycles. SMCLK provides clock source for TBCLK. During the TB\+\_\+0 ISR, P1.\+0 is toggled and 50000 clock cycles are added to CCR0. TB\+\_\+0 ISR is triggered every 50000 cycles. CPU is normally off and used only during TB\+\_\+\+ISR. ACLK = n/a, MCLK = SMCLK = TBCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex1__continuous_mode_c_c_r0_8c_autotoc_md75}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex1__continuous_mode_c_c_r0_8c_autotoc_md75}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex2__overflow_i_s_r_8c.tex
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@@ -19,7 +19,7 @@ void \mbox{\hyperlink{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex2__overflow_i_s
Timer\+\_\+B, Toggle P1.\+0, Overflow ISR, 32k\+Hz ACLK
Description\+: Toggle P1.\+0 using software and the Timer\+\_\+B overflow ISR. In this example an ISR triggers when TB overflows. Inside the ISR P1.\+0 is toggled. Toggle rate is exactly 0.\+25\+Hz = \mbox{[}32k\+Hz/\+FFFFh\mbox{]}/2. Proper use of the TBIV interrupt vector generator is demonstrated. ACLK = TBCLK = 32k\+Hz, MCLK = SMCLK = default DCO $\sim$ 1.\+045\+MHz\hypertarget{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex2__overflow_i_s_r_8c_autotoc_md72}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex2__overflow_i_s_r_8c_autotoc_md72}
Description\+: Toggle P1.\+0 using software and the Timer\+\_\+B overflow ISR. In this example an ISR triggers when TB overflows. Inside the ISR P1.\+0 is toggled. Toggle rate is exactly 0.\+25\+Hz = \mbox{[}32k\+Hz/\+FFFFh\mbox{]}/2. Proper use of the TBIV interrupt vector generator is demonstrated. ACLK = TBCLK = 32k\+Hz, MCLK = SMCLK = default DCO $\sim$ 1.\+045\+MHz\hypertarget{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex2__overflow_i_s_r_8c_autotoc_md76}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex2__overflow_i_s_r_8c_autotoc_md76}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex4__up_mode_operation_8c.tex
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@@ -24,7 +24,7 @@ void \mbox{\hyperlink{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex4__up_mode_oper
Timer\+\_\+B, Toggle P1.\+0, CCR0 Up Mode ISR, DCO SMCLK
Description\+: Toggle P1.\+0 using software and TB\+\_\+0 ISR. Timer\+\_\+B is configured for up mode, thus the timer overflows when TBR counts to CCR0. In this example, CCR0 is loaded with 50000. ACLK = n/a, MCLK = SMCLK = TBCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex4__up_mode_operation_8c_autotoc_md73}{}\doxysubsubsection{Tested On\+: MSP430\+F5229}\label{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex4__up_mode_operation_8c_autotoc_md73}
Description\+: Toggle P1.\+0 using software and TB\+\_\+0 ISR. Timer\+\_\+B is configured for up mode, thus the timer overflows when TBR counts to CCR0. In this example, CCR0 is loaded with 50000. ACLK = n/a, MCLK = SMCLK = TBCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex4__up_mode_operation_8c_autotoc_md77}{}\doxysubsubsection{Tested On\+: MSP430\+F5229}\label{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex4__up_mode_operation_8c_autotoc_md77}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex5__single_p_w_m_8c.tex
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@@ -34,7 +34,7 @@ Definition at line 64 of file timer\+\_\+b\+\_\+ex5\+\_\+single\+PWM.\+c.
Timer\+\_\+B, PWM TB0.\+1, Up Mode, DCO SMCLK
Description\+: This program generates PWM outputs on P5.\+7 using Timer\+\_\+B configured for up mode. The value , TIMER\+\_\+\+PERIOD, defines the PWM period and the value DUTY\+\_\+\+CYCLE the PWM duty cycle. Using $\sim$1.045MHz SMCLK as TBCLK, the timer period is $\sim$500us with a 75\% duty cycle on P5.\+7 ACLK = n/a, SMCLK = MCLK = TBCLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex5__single_p_w_m_8c_autotoc_md74}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex5__single_p_w_m_8c_autotoc_md74}
Description\+: This program generates PWM outputs on P5.\+7 using Timer\+\_\+B configured for up mode. The value , TIMER\+\_\+\+PERIOD, defines the PWM period and the value DUTY\+\_\+\+CYCLE the PWM duty cycle. Using $\sim$1.045MHz SMCLK as TBCLK, the timer period is $\sim$500us with a 75\% duty cycle on P5.\+7 ACLK = n/a, SMCLK = MCLK = TBCLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex5__single_p_w_m_8c_autotoc_md78}{}\doxysubsubsection{Tested On\+: MSP430\+F5529}\label{_m_s_p430_f5xx__6xx_2timer__b_2timer__b__ex5__single_p_w_m_8c_autotoc_md78}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2tlv_2tlv__ex1__get_device_type_8c.tex
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@@ -15,7 +15,7 @@ void \mbox{\hyperlink{_m_s_p430_f5xx__6xx_2tlv_2tlv__ex1__get_device_type_8c_acd
\doxysubsubsection{\texorpdfstring{main()}{main()}}
{\footnotesize\ttfamily void main (\begin{DoxyParamCaption}\item[{void}]{ }\end{DoxyParamCaption})}
tlv -\/ get\+Device\+Type\hypertarget{_m_s_p430_f5xx__6xx_2tlv_2tlv__ex1__get_device_type_8c_autotoc_md75}{}\doxysubsubsection{Tested on MSP430\+F5438\+A, MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2tlv_2tlv__ex1__get_device_type_8c_autotoc_md75}
tlv -\/ get\+Device\+Type\hypertarget{_m_s_p430_f5xx__6xx_2tlv_2tlv__ex1__get_device_type_8c_autotoc_md79}{}\doxysubsubsection{Tested on MSP430\+F5438\+A, MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2tlv_2tlv__ex1__get_device_type_8c_autotoc_md79}
/$\vert$$|$ $\vert$ $\vert$ $\vert$ $\vert$ --$\vert$ $\vert$ Device Type $\vert$ $\vert$ $\vert$ $\vert$
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2tlv_2tlv__ex2__read_t_l_v_descriptors_8c.tex
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@@ -441,7 +441,7 @@ Referenced by read\+ADCCAL().
The contents of TLV device descriptors are read out using the TLV functions and then stored into local variables.
ACLK = n/a, MCLK = SMCLK = default DCO $\sim$ 1.\+045\+MHz\hypertarget{_m_s_p430_f5xx__6xx_2tlv_2tlv__ex2__read_t_l_v_descriptors_8c_autotoc_md76}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969}\label{_m_s_p430_f5xx__6xx_2tlv_2tlv__ex2__read_t_l_v_descriptors_8c_autotoc_md76}
ACLK = n/a, MCLK = SMCLK = default DCO $\sim$ 1.\+045\+MHz\hypertarget{_m_s_p430_f5xx__6xx_2tlv_2tlv__ex2__read_t_l_v_descriptors_8c_autotoc_md80}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969}\label{_m_s_p430_f5xx__6xx_2tlv_2tlv__ex2__read_t_l_v_descriptors_8c_autotoc_md80}
/$\vert$$|$ XIN$\vert$-\/ $\vert$ $\vert$ $\vert$ --$\vert$\+RST XOUT$\vert$-\/ $\vert$ $\vert$ $\vert$ $\vert$
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex1__interval_s_m_c_l_k_8c.tex
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@@ -19,7 +19,7 @@ void \mbox{\hyperlink{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex1__interval_s_m_c_l
WDT -\/ Toggle P1.\+0, Interval Overflow ISR, DCO SMCLK
Toggle P1.\+0 using software timed by the WDT ISR. Toggle rate is approx. 30ms = \{(default DCO 1.\+045\+MHz) / 32768\} based on default DCO = SMCLK clock source used in this example for the WDT. ACLK = n/a, MCLK = SMCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex1__interval_s_m_c_l_k_8c_autotoc_md77}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex1__interval_s_m_c_l_k_8c_autotoc_md77}
Toggle P1.\+0 using software timed by the WDT ISR. Toggle rate is approx. 30ms = \{(default DCO 1.\+045\+MHz) / 32768\} based on default DCO = SMCLK clock source used in this example for the WDT. ACLK = n/a, MCLK = SMCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex1__interval_s_m_c_l_k_8c_autotoc_md81}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex1__interval_s_m_c_l_k_8c_autotoc_md81}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex2__interval_a_c_l_k_8c.tex
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@@ -19,7 +19,7 @@ void \mbox{\hyperlink{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex2__interval_a_c_l_k
WDT -\/ Toggle P1.\+0, Interval Overflow ISR, 32k\+Hz ACLK
Toggle P1.\+0 using software timed by WDT ISR. Toggle rate is exactly 250ms based on 32k\+Hz ACLK WDT clock source. In this example the WDT is configured to divide 32768 watch-\/crystal(2$^\wedge$15) by 2$^\wedge$13 with an ISR triggered @ 4Hz = \mbox{[}WDT CLK source/32768\mbox{]}. ACLK = REFO , MCLK = SMCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex2__interval_a_c_l_k_8c_autotoc_md78}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex2__interval_a_c_l_k_8c_autotoc_md78}
Toggle P1.\+0 using software timed by WDT ISR. Toggle rate is exactly 250ms based on 32k\+Hz ACLK WDT clock source. In this example the WDT is configured to divide 32768 watch-\/crystal(2$^\wedge$15) by 2$^\wedge$13 with an ISR triggered @ 4Hz = \mbox{[}WDT CLK source/32768\mbox{]}. ACLK = REFO , MCLK = SMCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex2__interval_a_c_l_k_8c_autotoc_md82}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex2__interval_a_c_l_k_8c_autotoc_md82}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex3__watchdog_a_c_l_k_8c.tex
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@@ -17,7 +17,7 @@ void \mbox{\hyperlink{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex3__watchdog_a_c_l_k
WDT -\/ Failsafe Clock, 10KHz VLOCLK
Configure WDT in watchdog to timeout sourced by ACLK. LPM3 is entered. This example will demonstrate WDT fail-\/safe feature by automatically selecting VLOCLK as WDT clock source if ACLK fails. Watchdog timeout will toggle on P1.\+0 every 3 seconds in main function. VLOCLK = 10KHZ, ACLK = 32768, MCLK = SMCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex3__watchdog_a_c_l_k_8c_autotoc_md79}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex3__watchdog_a_c_l_k_8c_autotoc_md79}
Configure WDT in watchdog to timeout sourced by ACLK. LPM3 is entered. This example will demonstrate WDT fail-\/safe feature by automatically selecting VLOCLK as WDT clock source if ACLK fails. Watchdog timeout will toggle on P1.\+0 every 3 seconds in main function. VLOCLK = 10KHZ, ACLK = 32768, MCLK = SMCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex3__watchdog_a_c_l_k_8c_autotoc_md83}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f5xx__6xx_2wdt__a_2wdt__a__ex3__watchdog_a_c_l_k_8c_autotoc_md83}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2crc_2crc__ex1__build_signature_8c.tex
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@@ -17,7 +17,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r2xx__4xx_2crc_2crc__ex1__build_signature_8c_a
CRC -\/ Build Signature and Rebuild to test.
The CRC is first used to build a signature using a seed and multiple data values. This signature is considered as the checksum and can be sent by a UART connection along with the data to verify the correct data has been sent. The second half of this program is used to test the CRC checksum of the data that has been created, by recreating the same checksum and comparing it to the first checksum. If the two checksum are equal, then P1.\+0 is set and the LED is turned on. Breakpoints can be set before the CRC\+\_\+set\+Data() function to observe the CRC register values and see the subsequent signatures before/after each data set.\hypertarget{_m_s_p430_f_r2xx__4xx_2crc_2crc__ex1__build_signature_8c_autotoc_md83}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r2xx__4xx_2crc_2crc__ex1__build_signature_8c_autotoc_md83}
The CRC is first used to build a signature using a seed and multiple data values. This signature is considered as the checksum and can be sent by a UART connection along with the data to verify the correct data has been sent. The second half of this program is used to test the CRC checksum of the data that has been created, by recreating the same checksum and comparing it to the first checksum. If the two checksum are equal, then P1.\+0 is set and the LED is turned on. Breakpoints can be set before the CRC\+\_\+set\+Data() function to observe the CRC register values and see the subsequent signatures before/after each data set.\hypertarget{_m_s_p430_f_r2xx__4xx_2crc_2crc__ex1__build_signature_8c_autotoc_md87}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r2xx__4xx_2crc_2crc__ex1__build_signature_8c_autotoc_md87}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 32x32 Signed Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RES0, RES1, RES2 and RES3.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md84}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md84}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md88}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md88}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 32x32 Signed Multiply Accumalate
Hardware multiplier is used to multiply-\/accumalate a set of numbers. The first calculation is automatically initiated after the second operand is loaded. A second multiply-\/accumulate operation is performed next. Results are stored in RES0, RES1, RES2 and RES3. SUMEXT contains the extended sign of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md85}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md85}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md89}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md89}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 32x32 Unsigned Multiply Accumalate
Hardware multiplier is used to multiply-\/accumalate a set of numbers. The first calculation is automatically initiated after the second operand is loaded. A second multiply-\/accumulate operation is performed next. Results are stored in RES0, RES1, RES2 and RES3. SUMEXT contains the extended sign of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md86}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md86}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md90}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md90}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex13__saturation_underflow_8c.tex
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@@ -45,7 +45,7 @@ MPY -\/ Saturation Mpode Underflow Test
Description\+: The example illustrates a special case showing underflow. Underflow occurs when adding 2 negative numbers yields a positive result. By having the saturation mode enabled, the result if rounded off to the highest negative number (0x8000.\+0000 for 16 bit). Results can be viewed in the debugger window.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex13__saturation_underflow_8c_autotoc_md87}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex13__saturation_underflow_8c_autotoc_md87}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex13__saturation_underflow_8c_autotoc_md91}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex13__saturation_underflow_8c_autotoc_md91}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex14__saturation_overflow_8c.tex
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@@ -45,7 +45,7 @@ MPY -\/ Saturation Mode Overflow Test
The example illustrates a special case showing overflow. The addition result of 2 positive numbers may exceed the highest positive number (0x7\+FFF FFFF for 32 bit result) due to overflow indicating a negative result. By having the saturation mode enabled, this result can be truncated off to this highest positive number. Results with and without saturation mode are shown.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex14__saturation_overflow_8c_autotoc_md88}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex14__saturation_overflow_8c_autotoc_md88}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex14__saturation_overflow_8c_autotoc_md92}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex14__saturation_overflow_8c_autotoc_md92}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex15__fraction_mode_8c.tex
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@@ -43,7 +43,7 @@ MPY -\/ Fractional mode, Q15 multiplication
The example illustrates multiplication of 2 Q15 numbers in fractional mode. The result is a Q15 (15 bit) number stored in the RES1 register. It can be viewed in the debugger window.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex15__fraction_mode_8c_autotoc_md89}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex15__fraction_mode_8c_autotoc_md89}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex15__fraction_mode_8c_autotoc_md93}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex15__fraction_mode_8c_autotoc_md93}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 16x16 Unsigned Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RESLO and RESHI.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c_autotoc_md90}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c_autotoc_md90}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c_autotoc_md94}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c_autotoc_md94}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 8x8 Unsigned Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RESLO and RESHI.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c_autotoc_md91}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c_autotoc_md91}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c_autotoc_md95}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c_autotoc_md95}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c.tex
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@@ -45,7 +45,7 @@ MPY -\/ 16x16 Signed Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RESLO, RESHI and SUMEXT = FFFF if result is negative, SUMEXT = 0 otherwise. Result is also stored as Result variable.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c_autotoc_md92}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c_autotoc_md92}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c_autotoc_md96}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c_autotoc_md96}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 8x8 Signed Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RESLO, RESHI and SUMEXT = FFFF if result is negative, SUMEXT = 0 otherwise.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c_autotoc_md93}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c_autotoc_md93}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c_autotoc_md97}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c_autotoc_md97}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 16x16 Unsigned Multiply Accumulate
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the carry of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c_autotoc_md94}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c_autotoc_md94}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c_autotoc_md98}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c_autotoc_md98}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c.tex
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@@ -17,7 +17,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex6__8bit_unsigned_mu
MPY -\/ 8x8 Unsigned Multiply Accumulate
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the carry of the result.\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c_autotoc_md95}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c_autotoc_md95}
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the carry of the result.\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c_autotoc_md99}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c_autotoc_md99}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 16x16 Signed Multiply Accumulate
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply-\/accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the extended sign of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c_autotoc_md96}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c_autotoc_md96}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c_autotoc_md100}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c_autotoc_md100}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 8x8 Signed Multiply Accumulate
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the extended sign of result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c_autotoc_md97}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c_autotoc_md97}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c_autotoc_md101}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c_autotoc_md101}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c.tex
View File

@@ -41,7 +41,7 @@ MPY -\/ 32x32 Unsigned Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RES0, RES1, RES2 and RES3.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c_autotoc_md98}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c_autotoc_md98}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c_autotoc_md102}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r2xx__4xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c_autotoc_md102}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2pmm_2pmm___reset___l_p_mx__5_8c.tex
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@@ -16,7 +16,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r2xx__4xx_2pmm_2pmm___reset___l_p_mx__5_8c_a62
\doxysubsubsection{\texorpdfstring{main()}{main()}}
{\footnotesize\ttfamily void main (\begin{DoxyParamCaption}\item[{void}]{ }\end{DoxyParamCaption})}
\hypertarget{_m_s_p430_f_r2xx__4xx_2pmm_2pmm___reset___l_p_mx__5_8c_autotoc_md99}{}\doxysubsubsection{MSP430\+FR2xx\+\_\+4xx Board}\label{_m_s_p430_f_r2xx__4xx_2pmm_2pmm___reset___l_p_mx__5_8c_autotoc_md99}
\hypertarget{_m_s_p430_f_r2xx__4xx_2pmm_2pmm___reset___l_p_mx__5_8c_autotoc_md103}{}\doxysubsubsection{MSP430\+FR2xx\+\_\+4xx Board}\label{_m_s_p430_f_r2xx__4xx_2pmm_2pmm___reset___l_p_mx__5_8c_autotoc_md103}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex1__pwm_single_8c.tex
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@@ -34,7 +34,7 @@ Definition at line 63 of file timer\+\_\+a\+\_\+ex1\+\_\+pwm\+Single.\+c.
Timer\+\_\+\+A3, PWM TA1.\+2, Up Mode, DCO SMCLK
Description\+: This program generates PWM outputs on P2.\+2 using Timer1\+\_\+A configured for up mode. The value , TIMER\+\_\+\+PERIOD, defines the PWM period and the value DUTY\+\_\+\+CYCLE the PWM duty cycle. Using $\sim$1.048MHz SMCLK as TACLK, the timer period is $\sim$480us with a 75\% duty cycle on P4.\+0 ACLK = n/a, SMCLK = MCLK = TACLK = default DCO $\sim$1.048MHz.\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex1__pwm_single_8c_autotoc_md100}{}\doxysubsubsection{Tested On\+: MSP430\+FR4133}\label{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex1__pwm_single_8c_autotoc_md100}
Description\+: This program generates PWM outputs on P2.\+2 using Timer1\+\_\+A configured for up mode. The value , TIMER\+\_\+\+PERIOD, defines the PWM period and the value DUTY\+\_\+\+CYCLE the PWM duty cycle. Using $\sim$1.048MHz SMCLK as TACLK, the timer period is $\sim$480us with a 75\% duty cycle on P4.\+0 ACLK = n/a, SMCLK = MCLK = TACLK = default DCO $\sim$1.048MHz.\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex1__pwm_single_8c_autotoc_md104}{}\doxysubsubsection{Tested On\+: MSP430\+FR4133}\label{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex1__pwm_single_8c_autotoc_md104}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c.tex
View File

@@ -19,7 +19,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex3__continous_
TIMER\+\_\+A, Toggle P1.\+0, Overflow ISR, 32k\+Hz ACLK
Description\+: Toggle P1.\+0 using software and the TIMER\+\_\+A overflow ISR. In this example an ISR triggers when TB overflows. Inside the ISR P1.\+0 is toggled. Toggle rate is exactly 0.\+25\+Hz = \mbox{[}32k\+Hz/\+FFFFh\mbox{]}/2. Proper use of the TAIV interrupt vector generator is demonstrated. ACLK = TBCLK = 32k\+Hz, MCLK = SMCLK = default DCO $\sim$ 1.\+048\+MHz\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c_autotoc_md101}{}\doxysubsubsection{Tested On\+: MSP430\+FR4133}\label{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c_autotoc_md101}
Description\+: Toggle P1.\+0 using software and the TIMER\+\_\+A overflow ISR. In this example an ISR triggers when TB overflows. Inside the ISR P1.\+0 is toggled. Toggle rate is exactly 0.\+25\+Hz = \mbox{[}32k\+Hz/\+FFFFh\mbox{]}/2. Proper use of the TAIV interrupt vector generator is demonstrated. ACLK = TBCLK = 32k\+Hz, MCLK = SMCLK = default DCO $\sim$ 1.\+048\+MHz\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c_autotoc_md105}{}\doxysubsubsection{Tested On\+: MSP430\+FR4133}\label{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c_autotoc_md105}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c.tex
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@@ -46,7 +46,7 @@ Definition at line 67 of file timer\+\_\+a\+\_\+ex4\+\_\+pwm\+Multiple\+Up\+Down
Timer\+\_\+\+A3, PWM TA1.\+1-\/2, Up/\+Down Mode, DCO SMCLK
Description\+: This program generates two PWM outputs on P4.\+0/8.3 using Timer1\+\_\+A configured for up/down mode. The value in CCR0, 128, defines the PWM period/2 and the values in CCR1 and CCR2 the PWM duty cycles. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$233us with a 75\% duty cycle on P4.\+0 and 25\% on P8.\+3. SMCLK = MCLK = TACLK = default DCO $\sim$1.048MHz.\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c_autotoc_md102}{}\doxysubsubsection{Tested On\+: MSP430\+FR4133}\label{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c_autotoc_md102}
Description\+: This program generates two PWM outputs on P4.\+0/8.3 using Timer1\+\_\+A configured for up/down mode. The value in CCR0, 128, defines the PWM period/2 and the values in CCR1 and CCR2 the PWM duty cycles. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$233us with a 75\% duty cycle on P4.\+0 and 25\% on P8.\+3. SMCLK = MCLK = TACLK = default DCO $\sim$1.048MHz.\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c_autotoc_md106}{}\doxysubsubsection{Tested On\+: MSP430\+FR4133}\label{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c_autotoc_md106}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c.tex
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@@ -44,7 +44,7 @@ Definition at line 64 of file timer\+\_\+a\+\_\+ex5\+\_\+pwm\+Multiple\+Up.\+c.
\doxysubsubsection{\texorpdfstring{TIMER\_PERIOD}{TIMER\_PERIOD}}
{\footnotesize\ttfamily \#define TIMER\+\_\+\+PERIOD~511}
This program generates two PWM outputs on P4.\+0, P8.\+3 using Timer1\+\_\+A configured for up mode. The value in CCR0, 512-\/1, defines the PWM period and the values in CCR1 and CCR2 the PWM duty cycles. Using $\sim$1.092MHz SMCLK as TACLK, the timer period is $\sim$500us with a 75\% duty cycle on P4.\+0 and 25\% on P8.\+3. ACLK = n/a, SMCLK = MCLK = TACLK = default DCO $\sim$1.048MHz.\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c_autotoc_md103}{}\doxysubsubsection{Tested On\+: MSP430\+FR4133}\label{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c_autotoc_md103}
This program generates two PWM outputs on P4.\+0, P8.\+3 using Timer1\+\_\+A configured for up mode. The value in CCR0, 512-\/1, defines the PWM period and the values in CCR1 and CCR2 the PWM duty cycles. Using $\sim$1.092MHz SMCLK as TACLK, the timer period is $\sim$500us with a 75\% duty cycle on P4.\+0 and 25\% on P8.\+3. ACLK = n/a, SMCLK = MCLK = TACLK = default DCO $\sim$1.048MHz.\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c_autotoc_md107}{}\doxysubsubsection{Tested On\+: MSP430\+FR4133}\label{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c_autotoc_md107}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c.tex
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@@ -32,7 +32,7 @@ Definition at line 64 of file timer\+\_\+a\+\_\+ex6\+\_\+up\+Down\+Mode\+Operati
\doxysubsubsection{\texorpdfstring{TIMER\_A\_PERIOD}{TIMER\_A\_PERIOD}}
{\footnotesize\ttfamily \#define TIMER\+\_\+\+A\+\_\+\+PERIOD~250}
Toggle P2.\+4 using hardware TA1.\+0 output. Timer1\+\_\+A is configured for up/down mode with CCR0 defining period, TA1.\+1 also output on P4.\+0. In this example, CCR0 is loaded with 250 and TA1.\+0 will toggle P4.\+0 at TACLK/2$\ast$250. Thus the output frequency on P4.\+0 will be the TACLK/500. No CPU or software resources required. As coded with TACLK = SMCLK, P4.\+0 output frequency is $\sim$1.048M/500. SMCLK = MCLK = TACLK = default DCO $\sim$1.048MHz\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c_autotoc_md104}{}\doxysubsubsection{Tested On\+: MSP430\+FR4133}\label{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c_autotoc_md104}
Toggle P2.\+4 using hardware TA1.\+0 output. Timer1\+\_\+A is configured for up/down mode with CCR0 defining period, TA1.\+1 also output on P4.\+0. In this example, CCR0 is loaded with 250 and TA1.\+0 will toggle P4.\+0 at TACLK/2$\ast$250. Thus the output frequency on P4.\+0 will be the TACLK/500. No CPU or software resources required. As coded with TACLK = SMCLK, P4.\+0 output frequency is $\sim$1.048M/500. SMCLK = MCLK = TACLK = default DCO $\sim$1.048MHz\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c_autotoc_md108}{}\doxysubsubsection{Tested On\+: MSP430\+FR4133}\label{_m_s_p430_f_r2xx__4xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c_autotoc_md108}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2timer__b_2timer__b__ex4__up_mode_operation_8c.tex
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@@ -24,7 +24,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r2xx__4xx_2timer__b_2timer__b__ex4__up_mode_op
Timer\+\_\+B, Toggle P1.\+0, CCR0 Up Mode ISR, DCO SMCLK
Description\+: Toggle P1.\+0 using software and TB\+\_\+0 ISR. Timer\+\_\+B is configured for up mode, thus the timer overflows when TBR counts to CCR0. In this example, CCR0 is loaded with 50000. ACLK = n/a, MCLK = SMCLK = TBCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__b_2timer__b__ex4__up_mode_operation_8c_autotoc_md105}{}\doxysubsubsection{Tested On\+: MSP430\+FR2311}\label{_m_s_p430_f_r2xx__4xx_2timer__b_2timer__b__ex4__up_mode_operation_8c_autotoc_md105}
Description\+: Toggle P1.\+0 using software and TB\+\_\+0 ISR. Timer\+\_\+B is configured for up mode, thus the timer overflows when TBR counts to CCR0. In this example, CCR0 is loaded with 50000. ACLK = n/a, MCLK = SMCLK = TBCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__b_2timer__b__ex4__up_mode_operation_8c_autotoc_md109}{}\doxysubsubsection{Tested On\+: MSP430\+FR2311}\label{_m_s_p430_f_r2xx__4xx_2timer__b_2timer__b__ex4__up_mode_operation_8c_autotoc_md109}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2timer__b_2timer__b__ex5__single_p_w_m_8c.tex
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@@ -34,7 +34,7 @@ Definition at line 64 of file timer\+\_\+b\+\_\+ex5\+\_\+single\+PWM.\+c.
Timer\+\_\+B, PWM TB0.\+1, Up Mode, DCO SMCLK
Description\+: This program generates PWM outputs on P2.\+6 using Timer\+\_\+B configured for up mode. The value , TIMER\+\_\+\+PERIOD, defines the PWM period and the value DUTY\+\_\+\+CYCLE the PWM duty cycle. Using $\sim$1.045MHz SMCLK as TBCLK, the timer period is $\sim$488us with a 75\% duty cycle on P2.\+6 ACLK = n/a, SMCLK = MCLK = TBCLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__b_2timer__b__ex5__single_p_w_m_8c_autotoc_md106}{}\doxysubsubsection{Tested On\+: MSP430\+FR2311}\label{_m_s_p430_f_r2xx__4xx_2timer__b_2timer__b__ex5__single_p_w_m_8c_autotoc_md106}
Description\+: This program generates PWM outputs on P2.\+6 using Timer\+\_\+B configured for up mode. The value , TIMER\+\_\+\+PERIOD, defines the PWM period and the value DUTY\+\_\+\+CYCLE the PWM duty cycle. Using $\sim$1.045MHz SMCLK as TBCLK, the timer period is $\sim$488us with a 75\% duty cycle on P2.\+6 ACLK = n/a, SMCLK = MCLK = TBCLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f_r2xx__4xx_2timer__b_2timer__b__ex5__single_p_w_m_8c_autotoc_md110}{}\doxysubsubsection{Tested On\+: MSP430\+FR2311}\label{_m_s_p430_f_r2xx__4xx_2timer__b_2timer__b__ex5__single_p_w_m_8c_autotoc_md110}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r2xx__4xx_2tlv_2tlv__ex1__get_device_type_8c.tex
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@@ -15,7 +15,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r2xx__4xx_2tlv_2tlv__ex1__get_device_type_8c_a
\doxysubsubsection{\texorpdfstring{main()}{main()}}
{\footnotesize\ttfamily void main (\begin{DoxyParamCaption}\item[{void}]{ }\end{DoxyParamCaption})}
tlv -\/ get\+Device\+Type\hypertarget{_m_s_p430_f_r2xx__4xx_2tlv_2tlv__ex1__get_device_type_8c_autotoc_md107}{}\doxysubsubsection{Tested on MSP430\+F5438\+A, MSP430\+FR5739}\label{_m_s_p430_f_r2xx__4xx_2tlv_2tlv__ex1__get_device_type_8c_autotoc_md107}
tlv -\/ get\+Device\+Type\hypertarget{_m_s_p430_f_r2xx__4xx_2tlv_2tlv__ex1__get_device_type_8c_autotoc_md111}{}\doxysubsubsection{Tested on MSP430\+F5438\+A, MSP430\+FR5739}\label{_m_s_p430_f_r2xx__4xx_2tlv_2tlv__ex1__get_device_type_8c_autotoc_md111}
/$\vert$$|$ $\vert$ $\vert$ $\vert$ $\vert$ --$\vert$ $\vert$ Device Type $\vert$ $\vert$ $\vert$ $\vert$
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2crc_2crc__ex1__build_signature_8c.tex
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@@ -17,7 +17,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r57xx_2crc_2crc__ex1__build_signature_8c_a6288
CRC -\/ Build Signature and Rebuild to test.
The CRC is first used to build a signature using a seed and multiple data values. This signature is considered as the checksum and can be sent by a UART connection along with the data to verify the correct data has been sent. The second half of this program is used to test the CRC checksum of the data that has been created, by recreating the same checksum and comparing it to the first checksum. If the two checksum are equal, then P1.\+0 is set and the LED is turned on. Breakpoints can be set before the CRC\+\_\+set\+Data() function to observe the CRC register values and see the subsequent signatures before/after each data set.\hypertarget{_m_s_p430_f_r57xx_2crc_2crc__ex1__build_signature_8c_autotoc_md109}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2crc_2crc__ex1__build_signature_8c_autotoc_md109}
The CRC is first used to build a signature using a seed and multiple data values. This signature is considered as the checksum and can be sent by a UART connection along with the data to verify the correct data has been sent. The second half of this program is used to test the CRC checksum of the data that has been created, by recreating the same checksum and comparing it to the first checksum. If the two checksum are equal, then P1.\+0 is set and the LED is turned on. Breakpoints can be set before the CRC\+\_\+set\+Data() function to observe the CRC register values and see the subsequent signatures before/after each data set.\hypertarget{_m_s_p430_f_r57xx_2crc_2crc__ex1__build_signature_8c_autotoc_md113}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2crc_2crc__ex1__build_signature_8c_autotoc_md113}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2dma_2dma__ex1__repeated_block_8c.tex
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@@ -17,7 +17,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r57xx_2dma_2dma__ex1__repeated_block_8c_a6288e
DMA -\/ Repeated Block Transfer to-\/and-\/from RAM, Software Trigger.
A 16 word block from 1C00-\/1\+C1\+Fh is transfered to 1C20h-\/1\+C3fh using DMA0 in a burst block using software DMAREQ trigger. After each transfer, source, destination and DMA size are reset to initial software setting because DMA transfer mode 5 is used. P1.\+0 is toggled during DMA transfer only for demonstration purposes. $\ast$$\ast$ RAM location 0x1\+C00 -\/ 0x1\+C3F used -\/ make sure no compiler conflict $\ast$$\ast$ ACLK = REFO = 32k\+Hz, MCLK = SMCLK = default DCO 1048576Hz\hypertarget{_m_s_p430_f_r57xx_2dma_2dma__ex1__repeated_block_8c_autotoc_md110}{}\doxysubsubsection{Tested on MSP430\+F5529, MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2dma_2dma__ex1__repeated_block_8c_autotoc_md110}
A 16 word block from 1C00-\/1\+C1\+Fh is transfered to 1C20h-\/1\+C3fh using DMA0 in a burst block using software DMAREQ trigger. After each transfer, source, destination and DMA size are reset to initial software setting because DMA transfer mode 5 is used. P1.\+0 is toggled during DMA transfer only for demonstration purposes. $\ast$$\ast$ RAM location 0x1\+C00 -\/ 0x1\+C3F used -\/ make sure no compiler conflict $\ast$$\ast$ ACLK = REFO = 32k\+Hz, MCLK = SMCLK = default DCO 1048576Hz\hypertarget{_m_s_p430_f_r57xx_2dma_2dma__ex1__repeated_block_8c_autotoc_md114}{}\doxysubsubsection{Tested on MSP430\+F5529, MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2dma_2dma__ex1__repeated_block_8c_autotoc_md114}
/$\vert$$|$ XIN$\vert$-\/ $\vert$ $\vert$ $\vert$ 32k\+Hz --$\vert$\+RST XOUT$\vert$-\/ $\vert$ $\vert$ $\vert$ P1.\+0$\vert$-\/$>$ LED $\vert$ $\vert$
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c.tex
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@@ -67,7 +67,7 @@ Definition at line 74 of file eusci\+\_\+a\+\_\+spi\+\_\+ex1\+\_\+slave.\+c.
SPI slave talks to SPI master using 3-\/wire mode. Data is received from master and data from slave is then transmitted back to master. USCI RX ISR is used to handle communication, CPU normally in LPM4. Prior to initial data exchange, master pulses slaves RST for complete reset.
Use with eusci\+\_\+spi\+\_\+ex1\+\_\+master code example. If the slave is in debug mode, the reset signal from the master will conflict with slave\textquotesingle{}s JTAG; to work around, use IAR\textquotesingle{}s \char`\"{}\+Release JTAG on Go\char`\"{} on slave device. If breakpoints are set in slave RX ISR, master must stopped also to avoid overrunning slave RXBUF.\hypertarget{_m_s_p430_f_r57xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c_autotoc_md111}{}\doxysubsubsection{Tesed on MSP430\+FR5969 and MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c_autotoc_md111}
Use with eusci\+\_\+spi\+\_\+ex1\+\_\+master code example. If the slave is in debug mode, the reset signal from the master will conflict with slave\textquotesingle{}s JTAG; to work around, use IAR\textquotesingle{}s \char`\"{}\+Release JTAG on Go\char`\"{} on slave device. If breakpoints are set in slave RX ISR, master must stopped also to avoid overrunning slave RXBUF.\hypertarget{_m_s_p430_f_r57xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c_autotoc_md115}{}\doxysubsubsection{Tesed on MSP430\+FR5969 and MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c_autotoc_md115}
/$\vert$\textbackslash{} $\vert$ $\vert$ $\vert$ $\vert$ $\vert$ Master---+-\/$>$$\vert$\+RST $\vert$ $\vert$ $\vert$ $\vert$ P2.\+0$\vert$-\/$>$ Data Out (UCA0\+SIMO) $\vert$ $\vert$ $\vert$ P2.\+1$\vert$$<$-\/ Data In (UCA0\+SOMI) $\vert$ $\vert$ $\vert$ P1.\+5$\vert$$<$-\/ Serial Clock Out (UCA0\+CLK)
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2eusci__b__spi_2eusci__b__spi__ex1__slave_8c.tex
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@@ -67,7 +67,7 @@ Definition at line 74 of file eusci\+\_\+b\+\_\+spi\+\_\+ex1\+\_\+slave.\+c.
SPI slave talks to SPI master using 3-\/wire mode. Data is received from master and data from slave is then transmitted back to master. USCI RX ISR is used to handle communication, CPU normally in LPM4. Prior to initial data exchange, master pulses slaves RST for complete reset.
Use with eusci\+\_\+spi\+\_\+ex1\+\_\+master code example. If the slave is in debug mode, the reset signal from the master will conflict with slave\textquotesingle{}s JTAG; to work around, use IAR\textquotesingle{}s \char`\"{}\+Release JTAG on Go\char`\"{} on slave device. If breakpoints are set in slave RX ISR, master must stopped also to avoid overrunning slave RXBUF.\hypertarget{_m_s_p430_f_r57xx_2eusci__b__spi_2eusci__b__spi__ex1__slave_8c_autotoc_md112}{}\doxysubsubsection{Tesed on MSP430\+FR5969 and MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2eusci__b__spi_2eusci__b__spi__ex1__slave_8c_autotoc_md112}
Use with eusci\+\_\+spi\+\_\+ex1\+\_\+master code example. If the slave is in debug mode, the reset signal from the master will conflict with slave\textquotesingle{}s JTAG; to work around, use IAR\textquotesingle{}s \char`\"{}\+Release JTAG on Go\char`\"{} on slave device. If breakpoints are set in slave RX ISR, master must stopped also to avoid overrunning slave RXBUF.\hypertarget{_m_s_p430_f_r57xx_2eusci__b__spi_2eusci__b__spi__ex1__slave_8c_autotoc_md116}{}\doxysubsubsection{Tesed on MSP430\+FR5969 and MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2eusci__b__spi_2eusci__b__spi__ex1__slave_8c_autotoc_md116}
/$\vert$\textbackslash{} $\vert$ $\vert$ $\vert$ $\vert$ $\vert$ Master---+-\/$>$$\vert$\+RST $\vert$ $\vert$ $\vert$ $\vert$ P1.\+6$\vert$-\/$>$ Data Out (UCB0\+SIMO) $\vert$ $\vert$ $\vert$ P1.\+7$\vert$$<$-\/ Data In (UCB0\+SOMI) $\vert$ $\vert$ $\vert$ P2.\+2$\vert$$<$-\/ Serial Clock Out (UCB0\+CLK)
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2framctl_2framctl__ex1__write_8c.tex
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@@ -22,7 +22,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r57xx_2framctl_2framctl__ex1__write_8c_a6288eb
Long word writes to FRAM
Description\+: Use long word write to write to 512 byte blocks of FRAM. Toggle LEDs after every 100 writes. NOTE\+: Running this example for extended periods will impact the FRAM endurance. ACLK = VLO, MCLK = SMCLK = 4MHz\hypertarget{_m_s_p430_f_r57xx_2framctl_2framctl__ex1__write_8c_autotoc_md113}{}\doxysubsubsection{Tested On\+: MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2framctl_2framctl__ex1__write_8c_autotoc_md113}
Description\+: Use long word write to write to 512 byte blocks of FRAM. Toggle LEDs after every 100 writes. NOTE\+: Running this example for extended periods will impact the FRAM endurance. ACLK = VLO, MCLK = SMCLK = 4MHz\hypertarget{_m_s_p430_f_r57xx_2framctl_2framctl__ex1__write_8c_autotoc_md117}{}\doxysubsubsection{Tested On\+: MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2framctl_2framctl__ex1__write_8c_autotoc_md117}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

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Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 32x32 Signed Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RES0, RES1, RES2 and RES3.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md114}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md114}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md118}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md118}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

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Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 32x32 Signed Multiply Accumalate
Hardware multiplier is used to multiply-\/accumalate a set of numbers. The first calculation is automatically initiated after the second operand is loaded. A second multiply-\/accumulate operation is performed next. Results are stored in RES0, RES1, RES2 and RES3. SUMEXT contains the extended sign of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md115}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md115}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md119}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md119}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 32x32 Unsigned Multiply Accumalate
Hardware multiplier is used to multiply-\/accumalate a set of numbers. The first calculation is automatically initiated after the second operand is loaded. A second multiply-\/accumulate operation is performed next. Results are stored in RES0, RES1, RES2 and RES3. SUMEXT contains the extended sign of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md116}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md116}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md120}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md120}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex13__saturation_underflow_8c.tex
View File

@@ -45,7 +45,7 @@ MPY -\/ Saturation Mpode Underflow Test
Description\+: The example illustrates a special case showing underflow. Underflow occurs when adding 2 negative numbers yields a positive result. By having the saturation mode enabled, the result if rounded off to the highest negative number (0x8000.\+0000 for 16 bit). Results can be viewed in the debugger window.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex13__saturation_underflow_8c_autotoc_md117}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex13__saturation_underflow_8c_autotoc_md117}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex13__saturation_underflow_8c_autotoc_md121}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex13__saturation_underflow_8c_autotoc_md121}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex14__saturation_overflow_8c.tex
View File

@@ -45,7 +45,7 @@ MPY -\/ Saturation Mode Overflow Test
The example illustrates a special case showing overflow. The addition result of 2 positive numbers may exceed the highest positive number (0x7\+FFF FFFF for 32 bit result) due to overflow indicating a negative result. By having the saturation mode enabled, this result can be truncated off to this highest positive number. Results with and without saturation mode are shown.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex14__saturation_overflow_8c_autotoc_md118}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex14__saturation_overflow_8c_autotoc_md118}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex14__saturation_overflow_8c_autotoc_md122}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex14__saturation_overflow_8c_autotoc_md122}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex15__fraction_mode_8c.tex
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@@ -43,7 +43,7 @@ MPY -\/ Fractional mode, Q15 multiplication
The example illustrates multiplication of 2 Q15 numbers in fractional mode. The result is a Q15 (15 bit) number stored in the RES1 register. It can be viewed in the debugger window.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex15__fraction_mode_8c_autotoc_md119}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex15__fraction_mode_8c_autotoc_md119}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex15__fraction_mode_8c_autotoc_md123}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex15__fraction_mode_8c_autotoc_md123}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 16x16 Unsigned Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RESLO and RESHI.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c_autotoc_md120}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c_autotoc_md120}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c_autotoc_md124}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex1__16bit_unsigned_multiply_8c_autotoc_md124}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 8x8 Unsigned Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RESLO and RESHI.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c_autotoc_md121}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c_autotoc_md121}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c_autotoc_md125}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex2__8bit_unsigned_multiply_8c_autotoc_md125}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c.tex
View File

@@ -45,7 +45,7 @@ MPY -\/ 16x16 Signed Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RESLO, RESHI and SUMEXT = FFFF if result is negative, SUMEXT = 0 otherwise. Result is also stored as Result variable.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c_autotoc_md122}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c_autotoc_md122}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c_autotoc_md126}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex3__16bit_signed_multiply_8c_autotoc_md126}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 8x8 Signed Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RESLO, RESHI and SUMEXT = FFFF if result is negative, SUMEXT = 0 otherwise.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c_autotoc_md123}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c_autotoc_md123}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c_autotoc_md127}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex4__8bit_signed_multiply_8c_autotoc_md127}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 16x16 Unsigned Multiply Accumulate
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the carry of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c_autotoc_md124}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c_autotoc_md124}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c_autotoc_md128}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex5__16bit_unsigned_multiply_accum_8c_autotoc_md128}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c.tex
View File

@@ -17,7 +17,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex6__8bit_unsigned_multip
MPY -\/ 8x8 Unsigned Multiply Accumulate
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the carry of the result.\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c_autotoc_md125}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c_autotoc_md125}
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the carry of the result.\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c_autotoc_md129}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex6__8bit_unsigned_multiply_accum_8c_autotoc_md129}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 16x16 Signed Multiply Accumulate
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply-\/accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the extended sign of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c_autotoc_md126}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c_autotoc_md126}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c_autotoc_md130}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex7__16bit_signed_multiply_accum_8c_autotoc_md130}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c.tex
View File

@@ -19,7 +19,7 @@ MPY -\/ 8x8 Signed Multiply Accumulate
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. A second multiply accumulate operation is performed after that. Results are stored in RESLO and RESHI. SUMEXT contains the extended sign of result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c_autotoc_md127}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c_autotoc_md127}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c_autotoc_md131}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex8__8bit_signed_multiply_accum_8c_autotoc_md131}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c.tex
View File

@@ -41,7 +41,7 @@ MPY -\/ 32x32 Unsigned Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RES0, RES1, RES2 and RES3.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c_autotoc_md128}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c_autotoc_md128}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c_autotoc_md132}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r57xx_2mpy32_2mpy32__ex9__32bit_unsigned_multiply_8c_autotoc_md132}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2rtc__b_2rtc__b__ex1__calendermode_8c.tex
View File

@@ -55,7 +55,7 @@ References \+\_\+\+\_\+no\+\_\+operation(), and new\+Time.
RTC\+\_\+B in Calendar mode, Interruptions every 1s, 1m, and 5th day of week at 5\+:00pm
This program demonstrates the RTC mode by triggering an interrupt every second and minute. This code toggles P1.\+0 every second. This code recommends an external LFXT1 crystal for RTC accuracy. Note that if XT1 is not present the code loops in an infinite loop. ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz\hypertarget{_m_s_p430_f_r57xx_2rtc__b_2rtc__b__ex1__calendermode_8c_autotoc_md129}{}\doxysubsubsection{Tested on\+: MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2rtc__b_2rtc__b__ex1__calendermode_8c_autotoc_md129}
This program demonstrates the RTC mode by triggering an interrupt every second and minute. This code toggles P1.\+0 every second. This code recommends an external LFXT1 crystal for RTC accuracy. Note that if XT1 is not present the code loops in an infinite loop. ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz\hypertarget{_m_s_p430_f_r57xx_2rtc__b_2rtc__b__ex1__calendermode_8c_autotoc_md133}{}\doxysubsubsection{Tested on\+: MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2rtc__b_2rtc__b__ex1__calendermode_8c_autotoc_md133}
/$\vert$\textbackslash{} $\vert$ XIN$\vert$-\/ $\vert$ $\vert$ $\vert$ 32k\+Hz ---$\vert$\+RST XOUT$\vert$-\/ $\vert$ $\vert$ $\vert$ P1.\+0 $\vert$-\/-\/$>$ Toggles every second $\vert$ $\vert$
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2timer__a_2timer__a__ex1__pwm_single_8c.tex
View File

@@ -34,7 +34,7 @@ Definition at line 63 of file timer\+\_\+a\+\_\+ex1\+\_\+pwm\+Single.\+c.
Timer\+\_\+\+A3, PWM TA1.\+2, Up Mode, DCO SMCLK
Description\+: This program generates PWM outputs on P2.\+2 using Timer1\+\_\+A configured for up mode. The value , TIMER\+\_\+\+PERIOD, defines the PWM period and the value DUTY\+\_\+\+CYCLE the PWM duty cycle. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$500us with a 75\% duty cycle on P2.\+2 ACLK = n/a, SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex1__pwm_single_8c_autotoc_md130}{}\doxysubsubsection{Tested On\+: MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex1__pwm_single_8c_autotoc_md130}
Description\+: This program generates PWM outputs on P2.\+2 using Timer1\+\_\+A configured for up mode. The value , TIMER\+\_\+\+PERIOD, defines the PWM period and the value DUTY\+\_\+\+CYCLE the PWM duty cycle. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$500us with a 75\% duty cycle on P2.\+2 ACLK = n/a, SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex1__pwm_single_8c_autotoc_md134}{}\doxysubsubsection{Tested On\+: MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex1__pwm_single_8c_autotoc_md134}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2timer__a_2timer__a__ex2__continous_mode_operation_with_c_c_r0_interrupt_8c.tex
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@@ -24,7 +24,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex2__continous_mode
TIMER\+\_\+A, Toggle P1.\+0, CCR0 Cont. Mode ISR, DCO SMCLK
Toggle P1.\+0 using software and TA\+\_\+0 ISR. Toggles every 50000 SMCLK cycles. SMCLK provides clock source for TACLK. During the TA\+\_\+0 ISR, P1.\+0 is toggled and 50000 clock cycles are added to CCR0. TA\+\_\+0 ISR is triggered every 50000 cycles. CPU is normally off and used only during TA\+\_\+\+ISR. ACLK = n/a, MCLK = SMCLK = TACLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex2__continous_mode_operation_with_c_c_r0_interrupt_8c_autotoc_md131}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex2__continous_mode_operation_with_c_c_r0_interrupt_8c_autotoc_md131}
Toggle P1.\+0 using software and TA\+\_\+0 ISR. Toggles every 50000 SMCLK cycles. SMCLK provides clock source for TACLK. During the TA\+\_\+0 ISR, P1.\+0 is toggled and 50000 clock cycles are added to CCR0. TA\+\_\+0 ISR is triggered every 50000 cycles. CPU is normally off and used only during TA\+\_\+\+ISR. ACLK = n/a, MCLK = SMCLK = TACLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex2__continous_mode_operation_with_c_c_r0_interrupt_8c_autotoc_md135}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex2__continous_mode_operation_with_c_c_r0_interrupt_8c_autotoc_md135}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c.tex
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@@ -19,7 +19,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex3__continous_mode
TIMER\+\_\+A, Toggle P1.\+0, Overflow ISR, 32k\+Hz ACLK
Description\+: Toggle P1.\+0 using software and the TIMER\+\_\+A overflow ISR. In this example an ISR triggers when TB overflows. Inside the ISR P1.\+0 is toggled. Toggle rate is exactly 0.\+25\+Hz = \mbox{[}32k\+Hz/\+FFFFh\mbox{]}/2. Proper use of the TAIV interrupt vector generator is demonstrated. ACLK = TBCLK = 32k\+Hz, MCLK = SMCLK = default DCO $\sim$ 1.\+045\+MHz\hypertarget{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c_autotoc_md132}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c_autotoc_md132}
Description\+: Toggle P1.\+0 using software and the TIMER\+\_\+A overflow ISR. In this example an ISR triggers when TB overflows. Inside the ISR P1.\+0 is toggled. Toggle rate is exactly 0.\+25\+Hz = \mbox{[}32k\+Hz/\+FFFFh\mbox{]}/2. Proper use of the TAIV interrupt vector generator is demonstrated. ACLK = TBCLK = 32k\+Hz, MCLK = SMCLK = default DCO $\sim$ 1.\+045\+MHz\hypertarget{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c_autotoc_md136}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex3__continous_mode_operation_with_t_a_i_e_interrupt_8c_autotoc_md136}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c.tex
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@@ -46,7 +46,7 @@ Definition at line 67 of file timer\+\_\+a\+\_\+ex4\+\_\+pwm\+Multiple\+Up\+Down
Timer\+\_\+\+A3, PWM TA1.\+1-\/2, Up/\+Down Mode, DCO SMCLK
Description\+: This program generates two PWM outputs on P2.\+2,3 using Timer1\+\_\+A configured for up/down mode. The value in CCR0, 128, defines the PWM period/2 and the values in CCR1 and CCR2 the PWM duty cycles. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$233us with a 75\% duty cycle on P2.\+2 and 25\% on P2.\+3. SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c_autotoc_md133}{}\doxysubsubsection{Tested On\+: MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c_autotoc_md133}
Description\+: This program generates two PWM outputs on P2.\+2,3 using Timer1\+\_\+A configured for up/down mode. The value in CCR0, 128, defines the PWM period/2 and the values in CCR1 and CCR2 the PWM duty cycles. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$233us with a 75\% duty cycle on P2.\+2 and 25\% on P2.\+3. SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c_autotoc_md137}{}\doxysubsubsection{Tested On\+: MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex4__pwm_multiple_up_down_8c_autotoc_md137}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c.tex
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@@ -44,7 +44,7 @@ Definition at line 64 of file timer\+\_\+a\+\_\+ex5\+\_\+pwm\+Multiple\+Up.\+c.
\doxysubsubsection{\texorpdfstring{TIMER\_PERIOD}{TIMER\_PERIOD}}
{\footnotesize\ttfamily \#define TIMER\+\_\+\+PERIOD~511}
This program generates two PWM outputs on P1.\+2,P1.\+3 using Timer1\+\_\+A configured for up mode. The value in CCR0, 512-\/1, defines the PWM period and the values in CCR1 and CCR2 the PWM duty cycles. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$500us with a 75\% duty cycle on P2.\+2 and 25\% on P2.\+3. ACLK = n/a, SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c_autotoc_md134}{}\doxysubsubsection{Tested On\+: MSP430\+FR5749}\label{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c_autotoc_md134}
This program generates two PWM outputs on P1.\+2,P1.\+3 using Timer1\+\_\+A configured for up mode. The value in CCR0, 512-\/1, defines the PWM period and the values in CCR1 and CCR2 the PWM duty cycles. Using $\sim$1.045MHz SMCLK as TACLK, the timer period is $\sim$500us with a 75\% duty cycle on P2.\+2 and 25\% on P2.\+3. ACLK = n/a, SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c_autotoc_md138}{}\doxysubsubsection{Tested On\+: MSP430\+FR5749}\label{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex5__pwm_multiple_up_8c_autotoc_md138}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c.tex
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@@ -32,7 +32,7 @@ Definition at line 65 of file timer\+\_\+a\+\_\+ex6\+\_\+up\+Down\+Mode\+Operati
\doxysubsubsection{\texorpdfstring{TIMER\_A\_PERIOD}{TIMER\_A\_PERIOD}}
{\footnotesize\ttfamily \#define TIMER\+\_\+\+A\+\_\+\+PERIOD~250}
Toggle P2.\+4 using hardware TA1.\+0 output. Timer1\+\_\+A is configured for up/down mode with CCR0 defining period, TA1.\+0 also output on P2.\+4. In this example, CCR0 is loaded with 250 and TA1.\+0 will toggle P2.\+4 at TACLK/2$\ast$250. Thus the output frequency on P2.\+4 will be the TACLK/1000. No CPU or software resources required. As coded with TACLK = SMCLK, P2.\+4 output frequency is $\sim$1.045M/1000. SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c_autotoc_md135}{}\doxysubsubsection{Tested On\+: MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c_autotoc_md135}
Toggle P2.\+4 using hardware TA1.\+0 output. Timer1\+\_\+A is configured for up/down mode with CCR0 defining period, TA1.\+0 also output on P2.\+4. In this example, CCR0 is loaded with 250 and TA1.\+0 will toggle P2.\+4 at TACLK/2$\ast$250. Thus the output frequency on P2.\+4 will be the TACLK/1000. No CPU or software resources required. As coded with TACLK = SMCLK, P2.\+4 output frequency is $\sim$1.045M/1000. SMCLK = MCLK = TACLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c_autotoc_md139}{}\doxysubsubsection{Tested On\+: MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2timer__a_2timer__a__ex6__up_down_mode_operation_8c_autotoc_md139}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2timer__b_2timer__b__ex4__up_mode_operation_8c.tex
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@@ -24,7 +24,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r57xx_2timer__b_2timer__b__ex4__up_mode_operat
Timer\+\_\+B, Toggle P1.\+0, CCR0 Up Mode ISR, DCO SMCLK
Description\+: Toggle P1.\+0 using software and TB\+\_\+0 ISR. Timer\+\_\+B is configured for up mode, thus the timer overflows when TBR counts to CCR0. In this example, CCR0 is loaded with 50000. ACLK = n/a, MCLK = SMCLK = TBCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r57xx_2timer__b_2timer__b__ex4__up_mode_operation_8c_autotoc_md136}{}\doxysubsubsection{Tested On\+: MSP430\+F5\+R5739}\label{_m_s_p430_f_r57xx_2timer__b_2timer__b__ex4__up_mode_operation_8c_autotoc_md136}
Description\+: Toggle P1.\+0 using software and TB\+\_\+0 ISR. Timer\+\_\+B is configured for up mode, thus the timer overflows when TBR counts to CCR0. In this example, CCR0 is loaded with 50000. ACLK = n/a, MCLK = SMCLK = TBCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r57xx_2timer__b_2timer__b__ex4__up_mode_operation_8c_autotoc_md140}{}\doxysubsubsection{Tested On\+: MSP430\+F5\+R5739}\label{_m_s_p430_f_r57xx_2timer__b_2timer__b__ex4__up_mode_operation_8c_autotoc_md140}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2timer__b_2timer__b__ex5__single_p_w_m_8c.tex
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@@ -34,7 +34,7 @@ Definition at line 64 of file timer\+\_\+b\+\_\+ex5\+\_\+single\+PWM.\+c.
Timer\+\_\+B, PWM TB0.\+1, Up Mode, DCO SMCLK
Description\+: This program generates PWM outputs on P1.\+4 using Timer\+\_\+B configured for up mode. The value , TIMER\+\_\+\+PERIOD, defines the PWM period and the value DUTY\+\_\+\+CYCLE the PWM duty cycle. Using $\sim$1.045MHz SMCLK as TBCLK, the timer period is $\sim$488us with a 75\% duty cycle on P1.\+4 ACLK = n/a, SMCLK = MCLK = TBCLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f_r57xx_2timer__b_2timer__b__ex5__single_p_w_m_8c_autotoc_md137}{}\doxysubsubsection{Tested On\+: MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2timer__b_2timer__b__ex5__single_p_w_m_8c_autotoc_md137}
Description\+: This program generates PWM outputs on P1.\+4 using Timer\+\_\+B configured for up mode. The value , TIMER\+\_\+\+PERIOD, defines the PWM period and the value DUTY\+\_\+\+CYCLE the PWM duty cycle. Using $\sim$1.045MHz SMCLK as TBCLK, the timer period is $\sim$488us with a 75\% duty cycle on P1.\+4 ACLK = n/a, SMCLK = MCLK = TBCLK = default DCO $\sim$1.045MHz.\hypertarget{_m_s_p430_f_r57xx_2timer__b_2timer__b__ex5__single_p_w_m_8c_autotoc_md141}{}\doxysubsubsection{Tested On\+: MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2timer__b_2timer__b__ex5__single_p_w_m_8c_autotoc_md141}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2tlv_2tlv__ex1__get_device_type_8c.tex
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@@ -15,7 +15,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r57xx_2tlv_2tlv__ex1__get_device_type_8c_acdef
\doxysubsubsection{\texorpdfstring{main()}{main()}}
{\footnotesize\ttfamily void main (\begin{DoxyParamCaption}\item[{void}]{ }\end{DoxyParamCaption})}
tlv -\/ get\+Device\+Type\hypertarget{_m_s_p430_f_r57xx_2tlv_2tlv__ex1__get_device_type_8c_autotoc_md138}{}\doxysubsubsection{Tested on MSP430\+F5438\+A, MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2tlv_2tlv__ex1__get_device_type_8c_autotoc_md138}
tlv -\/ get\+Device\+Type\hypertarget{_m_s_p430_f_r57xx_2tlv_2tlv__ex1__get_device_type_8c_autotoc_md142}{}\doxysubsubsection{Tested on MSP430\+F5438\+A, MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2tlv_2tlv__ex1__get_device_type_8c_autotoc_md142}
/$\vert$$|$ $\vert$ $\vert$ $\vert$ $\vert$ --$\vert$ $\vert$ Device Type $\vert$ $\vert$ $\vert$ $\vert$
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex1__interval_s_m_c_l_k_8c.tex
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@@ -19,7 +19,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex1__interval_s_m_c_l_k
WDT -\/ Toggle P1.\+0, Interval Overflow ISR, DCO SMCLK
Toggle P1.\+0 using software timed by the WDT ISR. Toggle rate is approx. 30ms = \{(default DCO 1.\+045\+MHz) / 32768\} based on default DCO = SMCLK clock source used in this example for the WDT. ACLK = n/a, MCLK = SMCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex1__interval_s_m_c_l_k_8c_autotoc_md139}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex1__interval_s_m_c_l_k_8c_autotoc_md139}
Toggle P1.\+0 using software timed by the WDT ISR. Toggle rate is approx. 30ms = \{(default DCO 1.\+045\+MHz) / 32768\} based on default DCO = SMCLK clock source used in this example for the WDT. ACLK = n/a, MCLK = SMCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex1__interval_s_m_c_l_k_8c_autotoc_md143}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex1__interval_s_m_c_l_k_8c_autotoc_md143}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex2__interval_a_c_l_k_8c.tex
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@@ -19,7 +19,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex2__interval_a_c_l_k_8
WDT -\/ Toggle P1.\+0, Interval Overflow ISR, 32k\+Hz ACLK
Toggle P1.\+0 using software timed by WDT ISR. Toggle rate is exactly 250ms based on 32k\+Hz ACLK WDT clock source. In this example the WDT is configured to divide 32768 watch-\/crystal(2$^\wedge$15) by 2$^\wedge$13 with an ISR triggered @ 4Hz = \mbox{[}WDT CLK source/32768\mbox{]}. ACLK = REFO , MCLK = SMCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex2__interval_a_c_l_k_8c_autotoc_md140}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex2__interval_a_c_l_k_8c_autotoc_md140}
Toggle P1.\+0 using software timed by WDT ISR. Toggle rate is exactly 250ms based on 32k\+Hz ACLK WDT clock source. In this example the WDT is configured to divide 32768 watch-\/crystal(2$^\wedge$15) by 2$^\wedge$13 with an ISR triggered @ 4Hz = \mbox{[}WDT CLK source/32768\mbox{]}. ACLK = REFO , MCLK = SMCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex2__interval_a_c_l_k_8c_autotoc_md144}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex2__interval_a_c_l_k_8c_autotoc_md144}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex3__watchdog_a_c_l_k_8c.tex
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@@ -17,7 +17,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex3__watchdog_a_c_l_k_8
WDT -\/ Failsafe Clock, 10KHz VLOCLK
Configure WDT in watchdog to timeout sourced by ACLK. LPM3 is entered. This example will demonstrate WDT fail-\/safe feature by automatically selecting VLOCLK as WDT clock source if ACLK fails. Watchdog timeout will toggle on P1.\+0 every 3 seconds in main function. VLOCLK = 10KHZ, ACLK = 32768, MCLK = SMCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex3__watchdog_a_c_l_k_8c_autotoc_md141}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex3__watchdog_a_c_l_k_8c_autotoc_md141}
Configure WDT in watchdog to timeout sourced by ACLK. LPM3 is entered. This example will demonstrate WDT fail-\/safe feature by automatically selecting VLOCLK as WDT clock source if ACLK fails. Watchdog timeout will toggle on P1.\+0 every 3 seconds in main function. VLOCLK = 10KHZ, ACLK = 32768, MCLK = SMCLK = default DCO $\sim$1.045MHz\hypertarget{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex3__watchdog_a_c_l_k_8c_autotoc_md145}{}\doxysubsubsection{Tested On\+: MSP430\+F5529,\+MSP430\+FR5739}\label{_m_s_p430_f_r57xx_2wdt__a_2wdt__a__ex3__watchdog_a_c_l_k_8c_autotoc_md145}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r5xx__6xx_2crc_2crc__ex1__build_signature_8c.tex
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@@ -17,7 +17,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r5xx__6xx_2crc_2crc__ex1__build_signature_8c_a
CRC -\/ Build Signature and Rebuild to test.
The CRC is first used to build a signature using a seed and multiple data values. This signature is considered as the checksum and can be sent by a UART connection along with the data to verify the correct data has been sent. The second half of this program is used to test the CRC checksum of the data that has been created, by recreating the same checksum and comparing it to the first checksum. If the two checksum are equal, then P1.\+0 is set and the LED is turned on. Breakpoints can be set before the CRC\+\_\+set\+Data() function to observe the CRC register values and see the subsequent signatures before/after each data set.\hypertarget{_m_s_p430_f_r5xx__6xx_2crc_2crc__ex1__build_signature_8c_autotoc_md142}{}\doxysubsubsection{Tested On\+: MSP430\+FR5969}\label{_m_s_p430_f_r5xx__6xx_2crc_2crc__ex1__build_signature_8c_autotoc_md142}
The CRC is first used to build a signature using a seed and multiple data values. This signature is considered as the checksum and can be sent by a UART connection along with the data to verify the correct data has been sent. The second half of this program is used to test the CRC checksum of the data that has been created, by recreating the same checksum and comparing it to the first checksum. If the two checksum are equal, then P1.\+0 is set and the LED is turned on. Breakpoints can be set before the CRC\+\_\+set\+Data() function to observe the CRC register values and see the subsequent signatures before/after each data set.\hypertarget{_m_s_p430_f_r5xx__6xx_2crc_2crc__ex1__build_signature_8c_autotoc_md146}{}\doxysubsubsection{Tested On\+: MSP430\+FR5969}\label{_m_s_p430_f_r5xx__6xx_2crc_2crc__ex1__build_signature_8c_autotoc_md146}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
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2
Generated Documentation/latex/_m_s_p430_f_r5xx__6xx_2dma_2dma__ex1__repeated_block_8c.tex
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@@ -17,7 +17,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r5xx__6xx_2dma_2dma__ex1__repeated_block_8c_a6
DMA -\/ Repeated Block Transfer to-\/and-\/from RAM, Software Trigger.
A 16 word block from 1C00-\/1\+C1\+Fh is transfered to 1C20h-\/1\+C3fh using DMA0 in a burst block using software DMAREQ trigger. After each transfer, source, destination and DMA size are reset to initial software setting because DMA transfer mode 5 is used. P1.\+0 is toggled during DMA transfer only for demonstration purposes. $\ast$$\ast$ RAM location 0x1\+C00 -\/ 0x1\+C3F used -\/ make sure no compiler conflict $\ast$$\ast$ ACLK = REFO = 32k\+Hz, MCLK = SMCLK = default DCO 1048576Hz\hypertarget{_m_s_p430_f_r5xx__6xx_2dma_2dma__ex1__repeated_block_8c_autotoc_md144}{}\doxysubsubsection{Tested on MSP430\+FR5969}\label{_m_s_p430_f_r5xx__6xx_2dma_2dma__ex1__repeated_block_8c_autotoc_md144}
A 16 word block from 1C00-\/1\+C1\+Fh is transfered to 1C20h-\/1\+C3fh using DMA0 in a burst block using software DMAREQ trigger. After each transfer, source, destination and DMA size are reset to initial software setting because DMA transfer mode 5 is used. P1.\+0 is toggled during DMA transfer only for demonstration purposes. $\ast$$\ast$ RAM location 0x1\+C00 -\/ 0x1\+C3F used -\/ make sure no compiler conflict $\ast$$\ast$ ACLK = REFO = 32k\+Hz, MCLK = SMCLK = default DCO 1048576Hz\hypertarget{_m_s_p430_f_r5xx__6xx_2dma_2dma__ex1__repeated_block_8c_autotoc_md148}{}\doxysubsubsection{Tested on MSP430\+FR5969}\label{_m_s_p430_f_r5xx__6xx_2dma_2dma__ex1__repeated_block_8c_autotoc_md148}
/$\vert$$|$ XIN$\vert$-\/ $\vert$ $\vert$ $\vert$ 32k\+Hz --$\vert$\+RST XOUT$\vert$-\/ $\vert$ $\vert$ $\vert$ P1.\+0$\vert$-\/$>$ LED $\vert$ $\vert$
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f_r5xx__6xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c.tex
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@@ -67,7 +67,7 @@ Definition at line 75 of file eusci\+\_\+a\+\_\+spi\+\_\+ex1\+\_\+slave.\+c.
SPI slave talks to SPI master using 3-\/wire mode. Data is received from master and data from slave is then transmitted back to master. USCI RX ISR is used to handle communication, CPU normally in LPM4. Prior to initial data exchange, master pulses slaves RST for complete reset.
Use with eusci\+\_\+spi\+\_\+ex1\+\_\+master code example. If the slave is in debug mode, the reset signal from the master will conflict with slave\textquotesingle{}s JTAG; to work around, use IAR\textquotesingle{}s \char`\"{}\+Release JTAG on Go\char`\"{} on slave device. If breakpoints are set in slave RX ISR, master must stopped also to avoid overrunning slave RXBUF.\hypertarget{_m_s_p430_f_r5xx__6xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c_autotoc_md145}{}\doxysubsubsection{Tesed on MSP430\+FR5969}\label{_m_s_p430_f_r5xx__6xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c_autotoc_md145}
Use with eusci\+\_\+spi\+\_\+ex1\+\_\+master code example. If the slave is in debug mode, the reset signal from the master will conflict with slave\textquotesingle{}s JTAG; to work around, use IAR\textquotesingle{}s \char`\"{}\+Release JTAG on Go\char`\"{} on slave device. If breakpoints are set in slave RX ISR, master must stopped also to avoid overrunning slave RXBUF.\hypertarget{_m_s_p430_f_r5xx__6xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c_autotoc_md149}{}\doxysubsubsection{Tesed on MSP430\+FR5969}\label{_m_s_p430_f_r5xx__6xx_2eusci__a__spi_2eusci__a__spi__ex1__slave_8c_autotoc_md149}
/$\vert$\textbackslash{} $\vert$ $\vert$ $\vert$ $\vert$ $\vert$ Master---+-\/$>$$\vert$\+RST $\vert$ $\vert$ $\vert$ $\vert$ P2.\+0$\vert$-\/$>$ Data Out (UCA0\+SIMO) $\vert$ $\vert$ $\vert$ P2.\+1$\vert$$<$-\/ Data In (UCA0\+SOMI) $\vert$ $\vert$ $\vert$ P1.\+5$\vert$$<$-\/ Serial Clock Out (UCA0\+CLK)
This example uses the following peripherals and I/O signals. You must review these and change as needed for your own board\+:

2
Generated Documentation/latex/_m_s_p430_f_r5xx__6xx_2framctl_2framctl__ex1__write_8c.tex
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@@ -17,7 +17,7 @@ void \mbox{\hyperlink{_m_s_p430_f_r5xx__6xx_2framctl_2framctl__ex1__write_8c_a62
Long word writes to FRAM
Description\+: Use long word write to write to 512 byte blocks of FRAM. Toggle LEDs after every 100 writes. NOTE\+: Running this example for extended periods will impact the FRAM endurance. ACLK = VLO, MCLK = SMCLK = 4MHz\hypertarget{_m_s_p430_f_r5xx__6xx_2framctl_2framctl__ex1__write_8c_autotoc_md146}{}\doxysubsubsection{Tested On\+: MSP430\+FR5969}\label{_m_s_p430_f_r5xx__6xx_2framctl_2framctl__ex1__write_8c_autotoc_md146}
Description\+: Use long word write to write to 512 byte blocks of FRAM. Toggle LEDs after every 100 writes. NOTE\+: Running this example for extended periods will impact the FRAM endurance. ACLK = VLO, MCLK = SMCLK = 4MHz\hypertarget{_m_s_p430_f_r5xx__6xx_2framctl_2framctl__ex1__write_8c_autotoc_md150}{}\doxysubsubsection{Tested On\+: MSP430\+FR5969}\label{_m_s_p430_f_r5xx__6xx_2framctl_2framctl__ex1__write_8c_autotoc_md150}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 32x32 Signed Multiply
Hardware multiplier is used to multiply two numbers. The calculation is automatically initiated after the second operand is loaded. Results are stored in RES0, RES1, RES2 and RES3.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md148}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md148}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md152}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex10__32bit_signed_multiply_8c_autotoc_md152}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 32x32 Signed Multiply Accumalate
Hardware multiplier is used to multiply-\/accumalate a set of numbers. The first calculation is automatically initiated after the second operand is loaded. A second multiply-\/accumulate operation is performed next. Results are stored in RES0, RES1, RES2 and RES3. SUMEXT contains the extended sign of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md149}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md149}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md153}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex11__32bit_signed_multiply_accum_8c_autotoc_md153}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

2
Generated Documentation/latex/_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c.tex
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@@ -19,7 +19,7 @@ MPY -\/ 32x32 Unsigned Multiply Accumalate
Hardware multiplier is used to multiply-\/accumalate a set of numbers. The first calculation is automatically initiated after the second operand is loaded. A second multiply-\/accumulate operation is performed next. Results are stored in RES0, RES1, RES2 and RES3. SUMEXT contains the extended sign of the result.
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md150}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md150}
ACLK = 32.\+768k\+Hz, MCLK = SMCLK = default DCO\hypertarget{_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md154}{}\doxysubsubsection{Tested On\+: MSP430\+F5438\+A,\+MSP430\+FR5739,\+MSP430\+FR5969,\+MSP430\+FR2433}\label{_m_s_p430_f_r5xx__6xx_2mpy32_2mpy32__ex12__32bit_unsigned_multiply_accum_8c_autotoc_md154}
\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{2}{|X[-1]}|}
\hline

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