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I believe the Debug_BlinkyLED-Advanced is now complete; need to test now

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This commit is contained in:
William Miceli
2021-05-18 12:57:24 -04:00
parent b719769971
commit 02d9ac3003
10 changed files with 230 additions and 65 deletions
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99
Telem_Debug/Debug_BlinkyLED-Advanced/clock_init.c
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@@ -14,17 +14,13 @@
*
*/
#include <msp430x54xa.h>
void Port_Init(void);
void Clock_XT1_Init(void);
void Clock_XT2_Init(void);
void SetVCoreUp(unsigned int level);
#include "SunseekerTelemetry2021.h"
#include "clock_init.h"
void clock_init(void)
{
WDTCTL = WDTPW + WDTHOLD; //Stop watchdog timer
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer; `WDTPW` is the "WatchDog Timer PassWord", required for all `WDTCTL` operations
Port_Init(); //ensure clock pins are configured
@@ -40,16 +36,16 @@ void clock_init(void)
void Port_Init(void)
{
//Clock Source TEST PINS ACLK/MCLK/SMCLK
P11DIR |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as output ACLK/MCLK/SMCLK
P11SEL |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as ACLK/MCLK/SMCLK function
P11DIR |= ACLK_TEST | MCLK_TEST | SMCLK_TEST; // Set P11.0:P11.2 as output ACLK/MCLK/SMCLK
P11SEL |= ACLK_TEST | MCLK_TEST | SMCLK_TEST; // Set P11.0:P11.2 as ACLK/MCLK/SMCLK function
//XT1 ALTERNATE PIN CONFIG
P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT peripheral
P7DIR |= (1 << 0) | (1 << 1);
P7SEL |= XT1IN | XT1OUT; // Set P7.0 & P7.1 as XT1IN/XT1OUT peripheral
P7DIR |= XT1IN | XT1OUT;
//XT2 ALTERNATE PIN CONFIG
P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT peripheral
P5DIR |= (1 << 2) | (1 << 3);
P5SEL |= XT2IN | XT2OUT; // Set P5.2 & P5.3 as XT2IN/XT2OUT peripheral
P5DIR |= XT2IN | XT2OUT;
}
void Clock_XT1_Init(void)
@@ -57,19 +53,20 @@ void Clock_XT1_Init(void)
char i;
//XT1 CLOCK CONFIG
UCSCTL6 &= ~(XT1OFF); //Enable XT1
UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0); //lowest drive current LF 32KHz oscillator
UCSCTL6 &= ~(XT1OFF); // Enable XT1
UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0); // Lowest drive current LF 32KHz oscillator
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; //Clear fault flags
for(i=255;i>0;i--); //Delay for Osc to stabilize
do{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
for(i=255;i>0;i--){ // Delay for oscillator to stabilize
_NOP(); // "No Operation"
}
}
while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag
while((SFRIFG1 & OFIFG) != 0); // Test oscillator fault flag
UCSCTL4 |= SELA__XT1CLK; //Clock Source ACLK = XT1 = 32kHz
UCSCTL5 |= DIVA_0; //Divide ACLK/1 = 32kHz
UCSCTL4 |= SELA__XT1CLK; // Clock Source ACLK = XT1 = 32kHz
UCSCTL5 |= DIVA_0; // Divide ACLK/1 = 32kHz
}
@@ -78,20 +75,21 @@ void Clock_XT2_Init(void)
char i;
//XT2 CLOCK CONFIG
UCSCTL6 &= ~(XT2OFF); //Enable XT2
UCSCTL6 |= XT2DRIVE_3; //Drive current 16-24 MHz Clock
UCSCTL6 &= ~XT2BYPASS; //XT2 Sourced Externally from pin - 20MHz
UCSCTL6 &= ~(XT2OFF); // Enable XT2
UCSCTL6 |= XT2DRIVE_3; // Drive current 16-24 MHz Clock
UCSCTL6 &= ~XT2BYPASS; // XT2 Sourced Externally from pin - 20MHz
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; //Clear fault flags
for(i=255;i>0;i--); //Delay for Osc to stabilize
do{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
for(i=255;i>0;i--){ // Delay for oscillator to stabilize
_NOP(); // "No Operation"
}
}
while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag
while((SFRIFG1 & OFIFG) != 0); // Test oscillator fault flag
UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK);//Clock Source SMCLK=MCLK = XT2 = 20MHz
UCSCTL5 |= DIVM_0 | DIVS_1; //MCLK:XT2/1 = 20MHz SMCLK:XT2/2 = 10MHz
UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK); // Clock Source SMCLK=MCLK = XT2 = 20MHz
UCSCTL5 |= DIVM_0 | DIVS_1; // MCLK:XT2/1 = 20MHz SMCLK:XT2/2 = 10MHz
}
@@ -105,25 +103,16 @@ void Clock_XT2_Init(void)
************************************************************/
void SetVCoreUp (unsigned int level)
{
// Open PMM registers for write access
PMMCTL0_H = 0xA5;
// Set SVS/SVM high side new level
SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
// Set SVM low side to new level
SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
// Wait till SVM is settled
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Clear already set flags
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
// Set VCore to new level
PMMCTL0_L = PMMCOREV0 * level;
// Wait till new level reached
if ((PMMIFG & SVMLIFG))
while ((PMMIFG & SVMLVLRIFG) == 0);
// Set SVS/SVM low side to new level
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
// Wait till SVM is settled
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Lock PMM registers for write access
PMMCTL0_H = 0x00;
PMMCTL0_H = 0xA5; // Open PMM registers for write access
SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level; // Set SVS/SVM high side new level
SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level; // Set SVM low side to new level
while((PMMIFG & SVSMLDLYIFG) == 0); // Wait till SVM is settled
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG); // Clear already set flags
PMMCTL0_L = PMMCOREV0 * level; // Set VCore to new level
if(PMMIFG & SVMLIFG){
while((PMMIFG & SVMLVLRIFG) == 0); // Wait till new level reached
}
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level; // Set SVS/SVM low side to new level
while((PMMIFG & SVSMLDLYIFG) == 0); // Wait till SVM is settled
PMMCTL0_H = 0x00; // Lock PMM registers for write access
}