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I believe the Debug_BlinkyLED-Advanced is now complete; need to test now

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This commit is contained in:
William Miceli
2021-05-18 12:57:24 -04:00
parent b719769971
commit 02d9ac3003
10 changed files with 230 additions and 65 deletions
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3
Telem_Debug/Debug_BlinkyLED-Advanced/SunseekerTelemetry2021.h
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@@ -9,7 +9,8 @@
* *
*/ */
#ifndef SUNSEEKERTELEMETRY2021_H_RY2021_H_SUNSEEKERTELEMETRY2021_H_ERTELEMETRY2021_H_ #ifndef SUNSEEKERTELEMETRY2021_H_
#define SUNSEEKERTELEMETRY2021_H_
#include <msp430x54xa.h> #include <msp430x54xa.h>
#include <stdio.h> #include <stdio.h>

99
Telem_Debug/Debug_BlinkyLED-Advanced/clock_init.c
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@@ -14,17 +14,13 @@
* *
*/ */
#include <msp430x54xa.h> #include <msp430x54xa.h>
#include "SunseekerTelemetry2021.h"
#include "clock_init.h"
void Port_Init(void);
void Clock_XT1_Init(void);
void Clock_XT2_Init(void);
void SetVCoreUp(unsigned int level);
void clock_init(void) void clock_init(void)
{ {
WDTCTL = WDTPW + WDTHOLD; //Stop watchdog timer WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer; `WDTPW` is the "WatchDog Timer PassWord", required for all `WDTCTL` operations
Port_Init(); //ensure clock pins are configured Port_Init(); //ensure clock pins are configured
@@ -40,16 +36,16 @@ void clock_init(void)
void Port_Init(void) void Port_Init(void)
{ {
//Clock Source TEST PINS ACLK/MCLK/SMCLK //Clock Source TEST PINS ACLK/MCLK/SMCLK
P11DIR |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as output ACLK/MCLK/SMCLK P11DIR |= ACLK_TEST | MCLK_TEST | SMCLK_TEST; // Set P11.0:P11.2 as output ACLK/MCLK/SMCLK
P11SEL |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as ACLK/MCLK/SMCLK function P11SEL |= ACLK_TEST | MCLK_TEST | SMCLK_TEST; // Set P11.0:P11.2 as ACLK/MCLK/SMCLK function
//XT1 ALTERNATE PIN CONFIG //XT1 ALTERNATE PIN CONFIG
P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT peripheral P7SEL |= XT1IN | XT1OUT; // Set P7.0 & P7.1 as XT1IN/XT1OUT peripheral
P7DIR |= (1 << 0) | (1 << 1); P7DIR |= XT1IN | XT1OUT;
//XT2 ALTERNATE PIN CONFIG //XT2 ALTERNATE PIN CONFIG
P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT peripheral P5SEL |= XT2IN | XT2OUT; // Set P5.2 & P5.3 as XT2IN/XT2OUT peripheral
P5DIR |= (1 << 2) | (1 << 3); P5DIR |= XT2IN | XT2OUT;
} }
void Clock_XT1_Init(void) void Clock_XT1_Init(void)
@@ -57,19 +53,20 @@ void Clock_XT1_Init(void)
char i; char i;
//XT1 CLOCK CONFIG //XT1 CLOCK CONFIG
UCSCTL6 &= ~(XT1OFF); //Enable XT1 UCSCTL6 &= ~(XT1OFF); // Enable XT1
UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0); //lowest drive current LF 32KHz oscillator UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0); // Lowest drive current LF 32KHz oscillator
do do{
{ UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags
SFRIFG1 &= ~OFIFG; //Clear fault flags for(i=255;i>0;i--){ // Delay for oscillator to stabilize
for(i=255;i>0;i--); //Delay for Osc to stabilize _NOP(); // "No Operation"
}
} }
while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag while((SFRIFG1 & OFIFG) != 0); // Test oscillator fault flag
UCSCTL4 |= SELA__XT1CLK; //Clock Source ACLK = XT1 = 32kHz UCSCTL4 |= SELA__XT1CLK; // Clock Source ACLK = XT1 = 32kHz
UCSCTL5 |= DIVA_0; //Divide ACLK/1 = 32kHz UCSCTL5 |= DIVA_0; // Divide ACLK/1 = 32kHz
} }
@@ -78,20 +75,21 @@ void Clock_XT2_Init(void)
char i; char i;
//XT2 CLOCK CONFIG //XT2 CLOCK CONFIG
UCSCTL6 &= ~(XT2OFF); //Enable XT2 UCSCTL6 &= ~(XT2OFF); // Enable XT2
UCSCTL6 |= XT2DRIVE_3; //Drive current 16-24 MHz Clock UCSCTL6 |= XT2DRIVE_3; // Drive current 16-24 MHz Clock
UCSCTL6 &= ~XT2BYPASS; //XT2 Sourced Externally from pin - 20MHz UCSCTL6 &= ~XT2BYPASS; // XT2 Sourced Externally from pin - 20MHz
do do{
{ UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags
SFRIFG1 &= ~OFIFG; //Clear fault flags for(i=255;i>0;i--){ // Delay for oscillator to stabilize
for(i=255;i>0;i--); //Delay for Osc to stabilize _NOP(); // "No Operation"
}
} }
while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag while((SFRIFG1 & OFIFG) != 0); // Test oscillator fault flag
UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK);//Clock Source SMCLK=MCLK = XT2 = 20MHz UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK); // Clock Source SMCLK=MCLK = XT2 = 20MHz
UCSCTL5 |= DIVM_0 | DIVS_1; //MCLK:XT2/1 = 20MHz SMCLK:XT2/2 = 10MHz UCSCTL5 |= DIVM_0 | DIVS_1; // MCLK:XT2/1 = 20MHz SMCLK:XT2/2 = 10MHz
} }
@@ -105,25 +103,16 @@ void Clock_XT2_Init(void)
************************************************************/ ************************************************************/
void SetVCoreUp (unsigned int level) void SetVCoreUp (unsigned int level)
{ {
// Open PMM registers for write access PMMCTL0_H = 0xA5; // Open PMM registers for write access
PMMCTL0_H = 0xA5; SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level; // Set SVS/SVM high side new level
// Set SVS/SVM high side new level SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level; // Set SVM low side to new level
SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level; while((PMMIFG & SVSMLDLYIFG) == 0); // Wait till SVM is settled
// Set SVM low side to new level PMMIFG &= ~(SVMLVLRIFG + SVMLIFG); // Clear already set flags
SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level; PMMCTL0_L = PMMCOREV0 * level; // Set VCore to new level
// Wait till SVM is settled if(PMMIFG & SVMLIFG){
while ((PMMIFG & SVSMLDLYIFG) == 0); while((PMMIFG & SVMLVLRIFG) == 0); // Wait till new level reached
// Clear already set flags }
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG); SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level; // Set SVS/SVM low side to new level
// Set VCore to new level while((PMMIFG & SVSMLDLYIFG) == 0); // Wait till SVM is settled
PMMCTL0_L = PMMCOREV0 * level; PMMCTL0_H = 0x00; // Lock PMM registers for write access
// Wait till new level reached
if ((PMMIFG & SVMLIFG))
while ((PMMIFG & SVMLVLRIFG) == 0);
// Set SVS/SVM low side to new level
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
// Wait till SVM is settled
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Lock PMM registers for write access
PMMCTL0_H = 0x00;
} }

9
Telem_Debug/Debug_BlinkyLED-Advanced/clock_init.h Normal file
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@@ -0,0 +1,9 @@
#ifndef CLOCK_INIT_H_
#define CLOCK_INIT_H_
void Port_Init(void);
void Clock_XT1_Init(void);
void Clock_XT2_Init(void);
void SetVCoreUp(unsigned int level);
#endif /* CLOCK_INIT_H_ */

28
Telem_Debug/Debug_BlinkyLED-Advanced/interrupts.c
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@@ -1,7 +1,31 @@
#include "SunseekerTelemetry2021.h"
#include "interrupts.h"
extern volatile unsigned char status_flag;
/* /*
* interrupts.c * Timer B CCR0 Interrupt Service Routine
* - Interrupts on Timer B CCR0 match at 10Hz
* - Sets Time_Flag variable
*/ */
/*
* GNU interrupt semantics
* interrupt(TIMERB0_VECTOR) timer_b0(void)
*/
#pragma vector = TIMERB0_VECTOR
__interrupt void timer_b0(void)
{
static unsigned int status_count = TELEM_STATUS_COUNT;
// Primary System Heart beat
status_count--;
if(status_count == 0){
status_count = TELEM_STATUS_COUNT;
status_flag = TRUE;
P8OUT &= ~LEDG; // Turn off the green LED
}else{
P8OUT |= LEDG; // Turn on the green LED
}
}

5
Telem_Debug/Debug_BlinkyLED-Advanced/interrupts.h
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@@ -1,12 +1,7 @@
/*
* interrupts.h
*/
#ifndef INTERRUPTS_H_ #ifndef INTERRUPTS_H_
#define INTERRUPTS_H_ #define INTERRUPTS_H_
#endif /* INTERRUPTS_H_ */ #endif /* INTERRUPTS_H_ */

103
Telem_Debug/Debug_BlinkyLED-Advanced/io_init.c Normal file
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@@ -0,0 +1,103 @@
/*
* I/O Initialization
*/
/*
* Initialize I/O port directions and states
* Drive unused pins as outputs to avoid floating inputs and wasting power
*
*/
#include "SunseekerTelemetry2021.h"
#include "io_init.h"
void io_init(void)
{
/******************************PORT 1**************************************/
P1OUT = 0x00; // Pull pins low, only affects ports set as output, no effect on inputs
P1DIR = P1_UNUSED; // Set to output
P1DIR &= ~(RTC_MFP | IMU_INTn); // Set to input
/*Interrupts Enable*/
// P1SEL = RTC_MFP | IMU_INTn;
// P1IE = RTC_MFP | IMU_INTn; // Enable Interrupts
P1IES = IMU_INTn; // High to low
P1IFG = 0x00; // Clear all interrupt flags on Port 1
delay();
/******************************PORT 2**************************************/
P2OUT = 0x00; // Pull pins low, only affects ports set as output, no effect on inputs
P2DIR = P2_UNUSED; // Set to output
/*Interrupts Enable */
// P2SEL = CAN0_INTn | CAN1_INTn | GPS_INTn; // Interrupts Select
// P2IES = CAN0_INTn | CAN1_INTn | GPS_INTn;
// P2IE = CAN0_INTn | CAN1_INTn | GPS_INTn; // Enable Interrupts
// P2SEL |= CAN0_RXB0n | CAN0_RXB1n | CAN1_RXB0n | CAN1_RXB1n; // Interrupts Select
// P2IES |= CAN0_RXB0n | CAN0_RXB1n | CAN1_RXB0n | CAN1_RXB1n;
// P2IE |= CAN0_RXB0n | CAN0_RXB1n | CAN1_RXB0n | CAN1_RXB1n; // Enable Interrupts
P2IFG = 0x00; // Clear all interrupt flags on Port 2
delay();
/******************************PORT 3**************************************/
P3OUT = 0x00; // Pull pins low, only affects ports set as output, no effect on inputs
P3DIR = CAN0_SCLK | CAN0_MOSI | SDC_SCLK | SDC_SIMO | CAN1_SCLK | P3_UNUSED; // Set to output
P3OUT |= CAN0_SCLK | CAN0_MOSI | SDC_SCLK | SDC_SIMO | CAN1_SCLK; // Pull used output pins high
P3DIR &= ~(CAN0_MISO | SDC_SOMI);
P3SEL = CAN0_SCLK | CAN0_MOSI | CAN0_MISO | SDC_SCLK | SDC_SIMO | SDC_SOMI | CAN1_SCLK | IMU_SDA;
/******************************PORT 4**************************************/
P4OUT = 0x00; // Pull pins low, only affects ports set as output, no effect on inputs
P4DIR = CAN0_RSTn | CAN0_CSn | CAN1_RSTn | CAN1_CSn | P4_UNUSED; // Set to output
P4OUT = CAN0_RSTn | CAN0_CSn | CAN1_RSTn | CAN1_CSn; // Pull used output pins high
delay();
P4OUT &= ~(CAN0_RSTn | CAN1_RSTn) ;
delay();
delay();
P4OUT |= (CAN0_RSTn | CAN1_RSTn) ;
/******************************PORT 5**************************************/
P5OUT = 0x00; // Pull pins low, only affects ports set as output, no effect on inputs
P5DIR = XT2OUT | CAN1_MOSI | P5_UNUSED;
P5OUT = CAN1_MOSI;
P5DIR &= ~(CAN1_MISO);
P5SEL = XT2IN | XT2OUT | IMU_SCL | CAN1_MOSI | CAN1_MISO;
/******************************PORT 6**************************************/
P6OUT = 0x00; // Pull pins low, only affects ports set as output, no effect on inputs
P6DIR = P6_UNUSED;
P6SEL = 0x00;
/******************************PORT 7**************************************/
P7OUT = 0x00; // Pull pins low, only affects ports set as output, no effect on inputs
P7DIR = XT1OUT | P7_UNUSED;
P7SEL = XT1IN | XT1OUT;
/******************************PORT 8**************************************/
P8OUT = 0x00; // Pull pins low, only affects ports set as output, no effect on inputs
P8DIR = LEDG | LEDR | LEDY0 | LEDY1 | P8_UNUSED;
P8DIR &= ~(Button0); // Set to input
P8SEL = 0x00;
/******************************PORT 9**************************************/
P9OUT = 0x00; // Pull pins low, only affects ports set as output, no effect on inputs
P9DIR = USB_TX | SDC_CSn | GPS_CSn | P9_UNUSED;
P9OUT = SDC_CSn | GPS_CSn;
P9SEL = RTC_SDA | RTC_SCL | USB_TX | USB_RX;
/******************************PORT 10**************************************/
P10OUT = 0x00; // Pull pins low, only affects ports set as output, no effect on inputs
P10DIR = BT_CSn | BT_MOSI | BT_SCLK | UART_TX | BT_EN |P10_UNUSED;
P10OUT = BT_CSn | BT_MOSI | BT_SCLK;
P10SEL = BT_MOSI | BT_MISO | BT_SCLK | UART_TX | UART_RX;
/******************************PORT 11**************************************/
P11OUT = 0x00; // Pull pins low, only affects ports set as output, no effect on inputs
P11DIR = ACLK_TEST | MCLK_TEST | SMCLK_TEST;
P11OUT = ACLK_TEST | MCLK_TEST | SMCLK_TEST;
P11SEL = ACLK_TEST | MCLK_TEST | SMCLK_TEST;
/******************************PORT J**************************************/
PJOUT = 0x00; // Pull pins low, only affects ports set as output, no effect on inputs
PJDIR = 0x0F; // Set to output as per user's guide
}

10
Telem_Debug/Debug_BlinkyLED-Advanced/io_init.h Normal file
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@@ -0,0 +1,10 @@
/*
* io_init.h
*/
#ifndef IO_INIT_H_
#define IO_INIT_H_
void io_init(void);
#endif /* IO_INIT_H_ */

16
Telem_Debug/Debug_BlinkyLED-Advanced/main.c
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@@ -3,6 +3,12 @@
*/ */
#include "SunseekerTelemetry2021.h" #include "SunseekerTelemetry2021.h"
#include "clock_init.h"
#include "interrupts.h"
#include "io_init.h"
#include "timers.h"
volatile unsigned char status_flag = FALSE;
int main(void) { int main(void) {
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer; `WDTPW` is the "WatchDog Timer PassWord", required for all `WDTCTL` operations WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer; `WDTPW` is the "WatchDog Timer PassWord", required for all `WDTCTL` operations
@@ -11,8 +17,14 @@ int main(void) {
clock_init(); // Configure HF and LF clocks clock_init(); // Configure HF and LF clocks
delay(); delay();
P8DIR = LEDG | LEDR | LEDY0 | LEDY1; // Set all four main LEDs as output timerB_init(); // Initialize timer B
P8OUT |= LEDG; // Turn on permanently the green LED delay();
io_init(); // Initialize all input/output pins
delay();
P8OUT &= ~LEDY0; // Initially set LEDY0 to High
P8OUT |= LEDY1; // Initially set LEDY1 to Low
_EINT(); //enable global interrupts _EINT(); //enable global interrupts

16
Telem_Debug/Debug_BlinkyLED-Advanced/timers.c Normal file
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@@ -0,0 +1,16 @@
/*
* Initialize Timer B
* - Provides timer tick timebase at 100 Hz
*/
#include "SunseekerTelemetry2021.h"
#include "timers.h"
void timerB_init(void)
{
TBCTL = CNTL_0 | TBSSEL_1 | ID_3 | TBCLR; // ACLK/8, clear TBR
TBCCR0 = (ACLK_RATE/8/TICK_RATE); // Set timer to count to this value = TICK_RATE overflow
TBCCTL0 = CCIE; // Enable CCR0 interrupt
TBCTL |= MC_1; // Set timer to 'up' count mode
}

6
Telem_Debug/Debug_BlinkyLED-Advanced/timers.h Normal file
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@@ -0,0 +1,6 @@
#ifndef TIMERS_H_
#define TIMERS_H_
void timerB_init(void);
#endif /* TIMERS_H_ */