William/Senior-Design-Project_WMU-Sunseeker_Code
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Comment fixes/consistency improvements

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This commit is contained in:
William Miceli
2021-05-14 15:30:32 -04:00
parent 148422b8a3
commit 8beec99a2d
3 changed files with 120 additions and 123 deletions
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11
Telem_Debug/Debug1/clock_init.c
View File

@@ -44,11 +44,11 @@ void Port_Init(void)
P11SEL |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as ACLK/MCLK/SMCLK function
//XT1 ALTERNATE PIN CONFIG
P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT periph
P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT peripheral
P7DIR |= (1 << 0) | (1 << 1);
//XT2 ALTERNATE PIN CONFIG
P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT periph
P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT peripheral
P5DIR |= (1 << 2) | (1 << 3);
}
@@ -80,7 +80,7 @@ void Clock_XT2_Init(void)
//XT2 CLOCK CONFIG
UCSCTL6 &= ~(XT2OFF); //Enable XT2
UCSCTL6 |= XT2DRIVE_3; //Drive current 16-24 MHz Clock
UCSCTL6 &= ~XT2BYPASS; //XT2 Sourced Externally from pin - 16MHz
UCSCTL6 &= ~XT2BYPASS; //XT2 Sourced Externally from pin - 20MHz
do
{
@@ -90,8 +90,8 @@ void Clock_XT2_Init(void)
}
while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag
UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK);//Clock Source SMCLK=MCLK = XT2 = 16MHz
UCSCTL5 |= DIVM_0 | DIVS_1; //MCLK:XT2/1 = 16MHz SMCLK:XT2/2 = 8MHz
UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK);//Clock Source SMCLK=MCLK = XT2 = 20MHz
UCSCTL5 |= DIVM_0 | DIVS_1; //MCLK:XT2/1 = 20MHz SMCLK:XT2/2 = 10MHz
}
@@ -127,4 +127,3 @@ void SetVCoreUp (unsigned int level)
// Lock PMM registers for write access
PMMCTL0_H = 0x00;
}

5
Telem_Debug/Debug2/clock_init.c
View File

@@ -44,11 +44,11 @@ void Port_Init(void)
P11SEL |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as ACLK/MCLK/SMCLK function
//XT1 ALTERNATE PIN CONFIG
P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT periph
P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT peripheral
P7DIR |= (1 << 0) | (1 << 1);
//XT2 ALTERNATE PIN CONFIG
P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT periph
P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT peripheral
P5DIR |= (1 << 2) | (1 << 3);
}
@@ -127,4 +127,3 @@ void SetVCoreUp (unsigned int level)
// Lock PMM registers for write access
PMMCTL0_H = 0x00;
}

5
Telem_Debug/Debug3/clock_init.c
View File

@@ -44,11 +44,11 @@ void Port_Init(void)
P11SEL |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as ACLK/MCLK/SMCLK function
//XT1 ALTERNATE PIN CONFIG
P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT periph
P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT peripheral
P7DIR |= (1 << 0) | (1 << 1);
//XT2 ALTERNATE PIN CONFIG
P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT periph
P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT peripheral
P5DIR |= (1 << 2) | (1 << 3);
}
@@ -127,4 +127,3 @@ void SetVCoreUp (unsigned int level)
// Lock PMM registers for write access
PMMCTL0_H = 0x00;
}